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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ | 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ |
| 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ | 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
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| 134 // code generator after register allocation which assembler method to call. | 134 // code generator after register allocation which assembler method to call. |
| 135 // | 135 // |
| 136 // We use the following local notation for addressing modes: | 136 // We use the following local notation for addressing modes: |
| 137 // | 137 // |
| 138 // R = register | 138 // R = register |
| 139 // O = register or stack slot | 139 // O = register or stack slot |
| 140 // D = double register | 140 // D = double register |
| 141 // I = immediate (handle, external, int32) | 141 // I = immediate (handle, external, int32) |
| 142 // MRI = [register + immediate] | 142 // MRI = [register + immediate] |
| 143 // MRR = [register + register] | 143 // MRR = [register + register] |
| 144 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 144 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 145 V(MRI) /* [%r0 + K] */ \ | 145 V(MRI) /* [%r0 + K] */ \ |
| 146 V(MRR) /* [%r0 + %r1] */ \ | 146 V(MRR) /* [%r0 + %r1] */ \ |
| 147 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ | 147 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ |
| 148 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ | 148 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ |
| 149 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ | 149 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ |
| 150 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ | 150 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ |
| 151 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ | 151 V(Operand2_R_UXTB) /* %r0 UXTB (unsigned extend byte) */ \ |
| 152 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ | 152 V(Operand2_R_UXTH) /* %r0 UXTH (unsigned extend halfword) */ \ |
| 153 V(Operand2_R_SXTB) /* %r0 SXTB (signed extend byte) */ \ |
| 154 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ |
| 153 | 155 |
| 154 } // namespace internal | 156 } // namespace internal |
| 155 } // namespace compiler | 157 } // namespace compiler |
| 156 } // namespace v8 | 158 } // namespace v8 |
| 157 | 159 |
| 158 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ | 160 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ |
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