MIPS: [turbofan] Add backend support for float32 operations.

MIPS: [turbofan] Add backend support for float32 operations.

Port 8dad78cdbd21c2cd02d6e0645313bd4b9983c78e

Original commit message:
This adds the basics necessary to support float32 operations in TurboFan.
The actual functionality required to detect safe float32 operations will
be added based on this later. Therefore this does not affect production
code except for some cleanup/refactoring.

In detail, this patchset contains the following features:
- Add support for float32 operations to arm, arm64, ia32 and x64
  backends.
- Add float32 machine operators.
- Add support for float32 constants to simplified lowering.
- Handle float32 representation for phis in simplified lowering.

In addition, contains the following (related) cleanups:
- Fix/unify naming of backend instructions.
- Use AVX comparisons when available.
- Extend ArchOpcodeField to 9 bits (required for arm64).
- Refactor some code duplication in instruction selectors.

BUG=v8:3589
LOG=n

Committed: https://crrev.com/dd402998f1adcd8c0413924bc8aea85955d8b878
Cr-Commit-Position: refs/heads/master@{#27531}

[balazs.kilvady, 2015-03-30 18:57:30]

balazs.kilvady@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, bmeurer@chromium.org, danno@chromium.org,
dusan.milosavljevic@imgtec.com, gergely.kis@imgtec.com, paul.lind@imgtec.com

[paul.l..., 2015-03-30 19:14:57]

LGTM.

[balazs.kilvady, 2015-03-30 19:15:21]

The CQ bit was checked by balazs.kilvady@imgtec.com

[commit-bot: I haz the power, 2015-03-30 19:15:32]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1046953004/1

[commit-bot: I haz the power, 2015-03-30 19:56:37]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2015-03-30 19:57:01]

Patchset 1 (id:??) landed as
https://crrev.com/dd402998f1adcd8c0413924bc8aea85955d8b878
Cr-Commit-Position: refs/heads/master@{#27531}