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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 1046953004: MIPS: [turbofan] Add backend support for float32 operations. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 16 matching lines...) Expand all
27 V(MipsOr) \ 27 V(MipsOr) \
28 V(MipsXor) \ 28 V(MipsXor) \
29 V(MipsClz) \ 29 V(MipsClz) \
30 V(MipsShl) \ 30 V(MipsShl) \
31 V(MipsShr) \ 31 V(MipsShr) \
32 V(MipsSar) \ 32 V(MipsSar) \
33 V(MipsRor) \ 33 V(MipsRor) \
34 V(MipsMov) \ 34 V(MipsMov) \
35 V(MipsTst) \ 35 V(MipsTst) \
36 V(MipsCmp) \ 36 V(MipsCmp) \
37 V(MipsCmpS) \
38 V(MipsAddS) \
39 V(MipsSubS) \
40 V(MipsMulS) \
41 V(MipsDivS) \
42 V(MipsModS) \
43 V(MipsSqrtS) \
37 V(MipsCmpD) \ 44 V(MipsCmpD) \
38 V(MipsAddD) \ 45 V(MipsAddD) \
39 V(MipsSubD) \ 46 V(MipsSubD) \
40 V(MipsMulD) \ 47 V(MipsMulD) \
41 V(MipsDivD) \ 48 V(MipsDivD) \
42 V(MipsModD) \ 49 V(MipsModD) \
43 V(MipsSqrtD) \ 50 V(MipsSqrtD) \
44 V(MipsFloat64RoundDown) \ 51 V(MipsFloat64RoundDown) \
45 V(MipsFloat64RoundTruncate) \ 52 V(MipsFloat64RoundTruncate) \
46 V(MipsFloat64RoundUp) \ 53 V(MipsFloat64RoundUp) \
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
89 #define TARGET_ADDRESSING_MODE_LIST(V) \ 96 #define TARGET_ADDRESSING_MODE_LIST(V) \
90 V(MRI) /* [%r0 + K] */ \ 97 V(MRI) /* [%r0 + K] */ \
91 V(MRR) /* [%r0 + %r1] */ 98 V(MRR) /* [%r0 + %r1] */
92 99
93 100
94 } // namespace compiler 101 } // namespace compiler
95 } // namespace internal 102 } // namespace internal
96 } // namespace v8 103 } // namespace v8
97 104
98 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 105 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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