MIPS: pre-crankshaft updates to macro-assembler and related files. (2/3)

MIPS: pre-crankshaft updates to macro-assembler and related files. (2/3)

Highlights:
- Better support for FP compares and branches (BranchF macro)
- Add EmitFPUTruncate() macro, similar to EmitVFPTruncate on Arm.
- Some improvements to long-branch mechanism for mips.
- Add ClampUint8() and ClampDoubleToUint8()

- Minor changes to ic-mips, full-codegen-mips mostly, for improved
code-patching with BinaryOpStub.
- Small changes to stack checking in full-codegen-mips and
regexp-macro-assembler-mips

BUG=
TEST=

Committed: http://code.google.com/p/v8/source/detail?r=9307

[Paul Lind, 2011-09-13 07:35:21]

Hmm, 2nd try on this one, did not get emailed or pushed to v8-dev list....

[danno, 2011-09-14 09:16:17]

Adding Erik to take a look at the instruction cache flushing. If this is really
the best alternative for MIPS, then the changes to src/assembler.h/.cc shouldn't
be #ifdefed for MIPS, even if unused on other platforms.

[danno, 2011-09-14 10:03:12]

I see the difference, on ARM inlining the values as internal reference is
probably slower than a constant pool load, so this style of internal reference
has never been implemented. I assume that you've measured the performance on
MIPS and it's better using internal reference?

Please remove the #ifdef around the assembler.h/.cc changes, since there's
nothing platform specific about them. Also, please move the icache flushing
changes to the third CL so that they are co-located with the code that uses
them.

[danno, 2011-09-14 10:03:12]

I see the difference, on ARM inlining the values as internal reference is
probably slower than a constant pool load, so this style of internal reference
has never been implemented. I assume that you've measured the performance on
MIPS and it's better using internal reference?

Please remove the #ifdef around the assembler.h/.cc changes, since there's
nothing platform specific about them. Also, please move the icache flushing
changes to the third CL so that they are co-located with the code that uses
them.

[Paul Lind, 2011-09-15 01:22:19]

Updated per your comments, removed the code-patching & cache-flushing (and
assembler.cc,h external references.) Will move all that to the remaining
changelist.

Regarding the inlining of the map constant, I will try to provide a little more
detail in separate email, but the short version is that mips does not have
pc-relative loads/stores like arm does, so we cannot use constant pools. We
inline all 32-bit constants into two instructions that load upper 16-bits and
'or' in lower 16-bits. These are LUI (load-upper-immediate) and ORI (or
immediate). Since these are in the instruction stream, we have to invalidate the
I-cache. 

Arm has similar instructions movt and movw, and some experimentation was done
long ago to replace constant pools there, by Erik, I think. It did not get used,
so I presume its slower. We borrowed some of his code/ideas to get our approach
working with relocating.

None of this directly uses INTERNAL_REFERENCES, but we do use those elsewhere.
Will explain in email.

[danno, 2011-09-16 09:08:21]

LGTM. I'll land this for you.