MIPS: pre-crankshaft updates to macro-assembler and related files. (2/3)

src/mips/ic-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1554 matching lines @@
 }
 
 
 void PatchInlinedSmiCode(Address address) {
   Address andi_instruction_address =
       address + Assembler::kCallTargetAddressOffset;
 
   // If the instruction following the call is not a andi at, rx, #yyy, nothing
   // was inlined.
   Instr instr = Assembler::instr_at(andi_instruction_address);
-  if (!Assembler::IsAndImmediate(instr)) {
+  if (!(Assembler::IsAndImmediate(instr) &&
+        Assembler::GetRt(instr) == (uint32_t)zero_reg.code())) {
     return;
   }
 
   // The delta to the start of the map check instruction and the
   // condition code uses at the patched jump.
   int delta = Assembler::GetImmediate16(instr);
   delta += Assembler::GetRs(instr) * kImm16Mask;
   // If the delta is 0 the instruction is andi at, zero_reg, #0 which also
   // signals that nothing was inlined.
   if (delta == 0) {
@@ skipping 40 matching lines @@
     Register reg = Register::from_code(Assembler::GetRs(instr_at_patch));
     patcher.masm()->andi(at, reg, kSmiTagMask);
     patcher.ChangeBranchCondition(eq);
   }
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS