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Unified Diff: src/mips/disasm-mips.cc

Issue 7888003: MIPS: pre-crankshaft updates to assembler and related files. (1/3) (Closed)
Patch Set: Created 9 years, 3 months ago
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Index: src/mips/disasm-mips.cc
diff --git a/src/mips/disasm-mips.cc b/src/mips/disasm-mips.cc
index 7df5c4175fda90f8a7737887009dc33014ff9675..fde0c58f081f2e56a84ec42543223cc22123cc0e 100644
--- a/src/mips/disasm-mips.cc
+++ b/src/mips/disasm-mips.cc
@@ -112,7 +112,7 @@ class Decoder {
void PrintUImm16(Instruction* instr);
void PrintSImm16(Instruction* instr);
void PrintXImm16(Instruction* instr);
- void PrintImm26(Instruction* instr);
+ void PrintXImm26(Instruction* instr);
void PrintCode(Instruction* instr); // For break and trap instructions.
// Printing of instruction name.
void PrintInstructionName(Instruction* instr);
@@ -273,9 +273,9 @@ void Decoder::PrintXImm16(Instruction* instr) {
// Print 26-bit immediate value.
-void Decoder::PrintImm26(Instruction* instr) {
- int32_t imm = instr->Imm26Value();
- out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
+void Decoder::PrintXImm26(Instruction* instr) {
+ uint32_t imm = instr->Imm26Value() << kImmFieldShift;
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}
@@ -383,9 +383,9 @@ int Decoder::FormatOption(Instruction* instr, const char* format) {
}
return 6;
} else {
- ASSERT(STRING_STARTS_WITH(format, "imm26"));
- PrintImm26(instr);
- return 5;
+ ASSERT(STRING_STARTS_WITH(format, "imm26x"));
+ PrintXImm26(instr);
+ return 6;
}
}
case 'r': { // 'r: registers.
@@ -926,10 +926,10 @@ void Decoder::DecodeTypeImmediate(Instruction* instr) {
void Decoder::DecodeTypeJump(Instruction* instr) {
switch (instr->OpcodeFieldRaw()) {
case J:
- Format(instr, "j 'imm26");
+ Format(instr, "j 'imm26x");
break;
case JAL:
- Format(instr, "jal 'imm26");
+ Format(instr, "jal 'imm26x");
break;
default:
UNREACHABLE();
@@ -958,6 +958,7 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
break;
}
default: {
+ Format(instr, "UNSUPPORTED");
UNSUPPORTED_MIPS();
}
}
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