| Index: src/mips/constants-mips.h
|
| diff --git a/src/mips/constants-mips.h b/src/mips/constants-mips.h
|
| index b20e9a284dff7ff713f4ee60f150f518482ebccb..eb0d22c2198d1bc6c2629d67e71fbecbd5052cba 100644
|
| --- a/src/mips/constants-mips.h
|
| +++ b/src/mips/constants-mips.h
|
| @@ -58,7 +58,7 @@ namespace v8 {
|
| namespace internal {
|
|
|
| // -----------------------------------------------------------------------------
|
| -// Registers and FPURegister.
|
| +// Registers and FPURegisters.
|
|
|
| // Number of general purpose registers.
|
| static const int kNumRegisters = 32;
|
| @@ -82,6 +82,11 @@ static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1;
|
| // FCSR constants.
|
| static const uint32_t kFCSRFlagMask = (1 << 6) - 1;
|
| static const uint32_t kFCSRFlagShift = 2;
|
| +static const uint32_t kFCSRInexactFlagBit = 1 << 0;
|
| +static const uint32_t kFCSRUnderflowFlagBit = 1 << 1;
|
| +static const uint32_t kFCSROverflowFlagBit = 1 << 2;
|
| +static const uint32_t kFCSRDivideByZeroFlagBit = 1 << 3;
|
| +static const uint32_t kFCSRInvalidOpFlagBit = 1 << 4;
|
|
|
| // Helper functions for converting between register numbers and names.
|
| class Registers {
|
| @@ -133,8 +138,6 @@ class FPURegisters {
|
| // On MIPS all instructions are 32 bits.
|
| typedef int32_t Instr;
|
|
|
| -typedef unsigned char byte_;
|
| -
|
| // Special Software Interrupt codes when used in the presence of the MIPS
|
| // simulator.
|
| enum SoftwareInterruptCodes {
|
| @@ -175,7 +178,7 @@ static const int kFBccBits = 3;
|
| static const int kFBtrueShift = 16;
|
| static const int kFBtrueBits = 1;
|
|
|
| -// ----- Miscellianous useful masks.
|
| +// ----- Miscellaneous useful masks.
|
| // Instruction bit masks.
|
| static const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
|
| static const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
|
| @@ -215,7 +218,7 @@ enum Opcode {
|
| XORI = ((1 << 3) + 6) << kOpcodeShift,
|
| LUI = ((1 << 3) + 7) << kOpcodeShift,
|
|
|
| - COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class
|
| + COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class.
|
| BEQL = ((2 << 3) + 4) << kOpcodeShift,
|
| BNEL = ((2 << 3) + 5) << kOpcodeShift,
|
| BLEZL = ((2 << 3) + 6) << kOpcodeShift,
|
| @@ -393,7 +396,7 @@ enum Condition {
|
|
|
| cc_always = 16,
|
|
|
| - // aliases
|
| + // Aliases.
|
| carry = Uless,
|
| not_carry = Ugreater_equal,
|
| zero = equal,
|
| @@ -455,14 +458,14 @@ inline Condition ReverseCondition(Condition cc) {
|
|
|
| // ----- Coprocessor conditions.
|
| enum FPUCondition {
|
| - F, // False
|
| - UN, // Unordered
|
| - EQ, // Equal
|
| - UEQ, // Unordered or Equal
|
| - OLT, // Ordered or Less Than
|
| - ULT, // Unordered or Less Than
|
| - OLE, // Ordered or Less Than or Equal
|
| - ULE // Unordered or Less Than or Equal
|
| + F, // False.
|
| + UN, // Unordered.
|
| + EQ, // Equal.
|
| + UEQ, // Unordered or Equal.
|
| + OLT, // Ordered or Less Than.
|
| + ULT, // Unordered or Less Than.
|
| + OLE, // Ordered or Less Than or Equal.
|
| + ULE // Unordered or Less Than or Equal.
|
| };
|
|
|
|
|
| @@ -494,7 +497,7 @@ extern const Instr kPopInstruction;
|
| extern const Instr kPushInstruction;
|
| // sw(r, MemOperand(sp, 0))
|
| extern const Instr kPushRegPattern;
|
| -// lw(r, MemOperand(sp, 0))
|
| +// lw(r, MemOperand(sp, 0))
|
| extern const Instr kPopRegPattern;
|
| extern const Instr kLwRegFpOffsetPattern;
|
| extern const Instr kSwRegFpOffsetPattern;
|
| @@ -687,7 +690,7 @@ class Instruction {
|
| // reference to an instruction is to convert a pointer. There is no way
|
| // to allocate or create instances of class Instruction.
|
| // Use the At(pc) function to create references to Instruction.
|
| - static Instruction* At(byte_* pc) {
|
| + static Instruction* At(byte* pc) {
|
| return reinterpret_cast<Instruction*>(pc);
|
| }
|
|
|
|
|