Update mips infrastructure files.

src/mips/constants-mips.h

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 40 matching lines @@
 // simulate MIPS32 instructions.
 //
 // See: MIPS32 Architecture For Programmers
 //      Volume II: The MIPS32 Instruction Set
 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf.
 
 namespace v8 {
 namespace internal {
 
 // -----------------------------------------------------------------------------
-// Registers and FPURegister.
+// Registers and FPURegisters.
 
 // Number of general purpose registers.
 static const int kNumRegisters = 32;
 static const int kInvalidRegister = -1;
 
 // Number of registers with HI, LO, and pc.
 static const int kNumSimuRegisters = 35;
 
 // In the simulator, the PC register is simulated as the 34th register.
 static const int kPCRegister = 34;
 
 // Number coprocessor registers.
 static const int kNumFPURegisters = 32;
 static const int kInvalidFPURegister = -1;
 
 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
 static const int kFCSRRegister = 31;
 static const int kInvalidFPUControlRegister = -1;
 static const uint32_t kFPUInvalidResult = (uint32_t) (1 << 31) - 1;
 
 // FCSR constants.
 static const uint32_t kFCSRFlagMask = (1 << 6) - 1;
 static const uint32_t kFCSRFlagShift = 2;
+static const uint32_t kFCSRInexactFlagBit = 1 << 0;
+static const uint32_t kFCSRUnderflowFlagBit = 1 << 1;
+static const uint32_t kFCSROverflowFlagBit = 1 << 2;
+static const uint32_t kFCSRDivideByZeroFlagBit = 1 << 3;
+static const uint32_t kFCSRInvalidOpFlagBit = 1 << 4;
 
 // Helper functions for converting between register numbers and names.
 class Registers {
  public:
   // Return the name of the register.
   static const char* Name(int reg);
 
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
@@ skipping 31 matching lines @@
   static const RegisterAlias aliases_[];
 };
 
 
 // -----------------------------------------------------------------------------
 // Instructions encoding constants.
 
 // On MIPS all instructions are 32 bits.
 typedef int32_t Instr;
 
-typedef unsigned char byte_;
-
 // Special Software Interrupt codes when used in the presence of the MIPS
 // simulator.
 enum SoftwareInterruptCodes {
   // Transition to C code.
   call_rt_redirected = 0xfffff
 };
 
 // ----- Fields offset and length.
 static const int kOpcodeShift   = 26;
 static const int kOpcodeBits    = 6;
@@ skipping 20 matching lines @@
 static const int kFtBits        = 5;
 static const int kFdShift       = 6;
 static const int kFdBits        = 5;
 static const int kFCccShift     = 8;
 static const int kFCccBits      = 3;
 static const int kFBccShift     = 18;
 static const int kFBccBits      = 3;
 static const int kFBtrueShift   = 16;
 static const int kFBtrueBits    = 1;
 
-// ----- Miscellianous useful masks.
+// ----- Miscellaneous useful masks.
 // Instruction bit masks.
 static const int  kOpcodeMask   = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
 static const int  kImm16Mask    = ((1 << kImm16Bits) - 1) << kImm16Shift;
 static const int  kImm26Mask    = ((1 << kImm26Bits) - 1) << kImm26Shift;
 static const int  kRsFieldMask  = ((1 << kRsBits) - 1) << kRsShift;
 static const int  kRtFieldMask  = ((1 << kRtBits) - 1) << kRtShift;
 static const int  kRdFieldMask  = ((1 << kRdBits) - 1) << kRdShift;
 static const int  kSaFieldMask  = ((1 << kSaBits) - 1) << kSaShift;
 static const int  kFunctionFieldMask =
     ((1 << kFunctionBits) - 1) << kFunctionShift;
@@ skipping 19 matching lines @@
 
   ADDI      =   ((1 << 3) + 0) << kOpcodeShift,
   ADDIU     =   ((1 << 3) + 1) << kOpcodeShift,
   SLTI      =   ((1 << 3) + 2) << kOpcodeShift,
   SLTIU     =   ((1 << 3) + 3) << kOpcodeShift,
   ANDI      =   ((1 << 3) + 4) << kOpcodeShift,
   ORI       =   ((1 << 3) + 5) << kOpcodeShift,
   XORI      =   ((1 << 3) + 6) << kOpcodeShift,
   LUI       =   ((1 << 3) + 7) << kOpcodeShift,
 
-  COP1      =   ((2 << 3) + 1) << kOpcodeShift,  // Coprocessor 1 class
+  COP1      =   ((2 << 3) + 1) << kOpcodeShift,  // Coprocessor 1 class.
   BEQL      =   ((2 << 3) + 4) << kOpcodeShift,
   BNEL      =   ((2 << 3) + 5) << kOpcodeShift,
   BLEZL     =   ((2 << 3) + 6) << kOpcodeShift,
   BGTZL     =   ((2 << 3) + 7) << kOpcodeShift,
 
   SPECIAL2  =   ((3 << 3) + 4) << kOpcodeShift,
   SPECIAL3  =   ((3 << 3) + 7) << kOpcodeShift,
 
   LB        =   ((4 << 3) + 0) << kOpcodeShift,
   LH        =   ((4 << 3) + 1) << kOpcodeShift,
@@ skipping 157 matching lines @@
   positive      =  9,
   parity_even   = 10,
   parity_odd    = 11,
   less          = 12,
   greater_equal = 13,
   less_equal    = 14,
   greater       = 15,
 
   cc_always     = 16,
 
-  // aliases
+  // Aliases.
   carry         = Uless,
   not_carry     = Ugreater_equal,
   zero          = equal,
   eq            = equal,
   not_zero      = not_equal,
   ne            = not_equal,
   nz            = not_equal,
   sign          = negative,
   not_sign      = positive,
   mi            = negative,
@@ skipping 41 matching lines @@
     case less_equal:
       return greater_equal;
     default:
       return cc;
   };
 }
 
 
 // ----- Coprocessor conditions.
 enum FPUCondition {
-  F,    // False
-  UN,   // Unordered
-  EQ,   // Equal
-  UEQ,  // Unordered or Equal
-  OLT,  // Ordered or Less Than
-  ULT,  // Unordered or Less Than
-  OLE,  // Ordered or Less Than or Equal
-  ULE   // Unordered or Less Than or Equal
+  F,    // False.
+  UN,   // Unordered.
+  EQ,   // Equal.
+  UEQ,  // Unordered or Equal.
+  OLT,  // Ordered or Less Than.
+  ULT,  // Unordered or Less Than.
+  OLE,  // Ordered or Less Than or Equal.
+  ULE   // Unordered or Less Than or Equal.
 };
 
 
 // -----------------------------------------------------------------------------
 // Hints.
 
 // Branch hints are not used on the MIPS.  They are defined so that they can
 // appear in shared function signatures, but will be ignored in MIPS
 // implementations.
 enum Hint {
@@ skipping 11 matching lines @@
 // These constants are declared in assembler-mips.cc, as they use named
 // registers and other constants.
 
 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
 // operations as post-increment of sp.
 extern const Instr kPopInstruction;
 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
 extern const Instr kPushInstruction;
 // sw(r, MemOperand(sp, 0))
 extern const Instr kPushRegPattern;
-//  lw(r, MemOperand(sp, 0))
+// lw(r, MemOperand(sp, 0))
 extern const Instr kPopRegPattern;
 extern const Instr kLwRegFpOffsetPattern;
 extern const Instr kSwRegFpOffsetPattern;
 extern const Instr kLwRegFpNegOffsetPattern;
 extern const Instr kSwRegFpNegOffsetPattern;
 // A mask for the Rt register for push, pop, lw, sw instructions.
 extern const Instr kRtMask;
 extern const Instr kLwSwInstrTypeMask;
 extern const Instr kLwSwInstrArgumentMask;
 extern const Instr kLwSwOffsetMask;
@@ skipping 172 matching lines @@
   bool IsForbiddenInBranchDelay() const;
   // Say if the instruction 'links'. eg: jal, bal.
   bool IsLinkingInstruction() const;
   // Say if the instruction is a break or a trap.
   bool IsTrap() const;
 
   // Instructions are read of out a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instruction.
   // Use the At(pc) function to create references to Instruction.
-  static Instruction* At(byte_* pc) {
+  static Instruction* At(byte* pc) {
     return reinterpret_cast<Instruction*>(pc);
   }
 
  private:
   // We need to prevent the creation of instances of class Instruction.
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
 };
 
 
 // -----------------------------------------------------------------------------
@@ skipping 13 matching lines @@
 
 static const int kDoubleAlignmentBits = 3;
 static const int kDoubleAlignment = (1 << kDoubleAlignmentBits);
 static const int kDoubleAlignmentMask = kDoubleAlignment - 1;
 
 
 } }   // namespace v8::internal
 
 #endif    // #ifndef V8_MIPS_CONSTANTS_H_