Revert MMIO space writes on shutdown as needed.

nicintel_spi.c

Index: nicintel_spi.c
diff --git a/nicintel_spi.c b/nicintel_spi.c
index 2d2d5b22d200e14f95232105d5cd4760bbcf80f0..f6eb5ebccf5f1b1d06733ad41ab979f98320e09a 100644
--- a/nicintel_spi.c
+++ b/nicintel_spi.c
@@ -149,6 +149,7 @@ int nicintel_spi_init(void)
 
 	nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
 				  io_base_addr, 4096);
+	/* Automatic restore is not possible because we only change two bits. */

[Stefan Reinauer, 2011/04/19 18:24:55]

Why are two bits not enough?

[Louis, 2011/04/20 00:43:55]

Hm.... I don't the exact reason, I just patch this from patchwork CL. I will
remove this before submit.

On 2011/04/19 18:24:55, Stefan Reinauer wrote:

[dhendrix, 2011/04/20 00:55:25]

Agreed -- Removing the comment is probably best to avoid confusion. I believe
the author meant that restoring this register is simply a bad idea, since it
contains a lot of other SPI-related state (CLock, CS, MISO, MOSI) that should
only be set as-needed.

 	tmp = pci_mmio_readl(nicintel_spibar + EECD);
 	tmp &= ~FLASH_WRITES_DISABLED;
 	tmp |= FLASH_WRITES_ENABLED;
@@ -168,6 +169,7 @@ int nicintel_spi_shutdown(void)
 {
 	uint32_t tmp;
 
+	/* Automatic restore is not possible because we only change two bits. */
 	tmp = pci_mmio_readl(nicintel_spibar + EECD);
 	tmp &= ~FLASH_WRITES_ENABLED;
 	tmp |= FLASH_WRITES_DISABLED;