CHROMIUM: tegra: seaboard: fix ULPI transceiver clock

CHROMIUM: tegra: seaboard: fix ULPI transceiver clock

On our seaboard-based platforms, pll_p_out4 is used to clock
(through DAP_MCLK2) the external USB ULPI transceiver between the USB2
port to mini-PCIe modem. And it needs to be set at 24Mhz for the
tranceiver to work correctly.
Revert the sclk parent to pll_c out1 (as it was before the last change)
since it needs to stay clocked at 108MHz.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>;

BUG=chrome-os-partner:3167
TEST=Check that the Gobi modem is appearing in lsusb listing
Use the kaen DVT for browsing and suspending

Committed: http://chrome-svn/viewvc/chromeos?view=rev&revision=dfb625f

[Vincent Palatin, 2011-04-12 15:28:25]

This patch aims at getting the 3G modem back in a functional state on the Kaen
board.

It partially reverts the commit 4d33c7b4a503eca8437c00a3b3a861122d397941
(
http://git.chromium.org/gitweb/?p=kernel-next.git;a=commitdiff;h=4d33c7b4a503...
)
I have asked Danny that change, here is his answer :
"When we're bringing up the emc scaling functionality on seaboard, there is a
video playback hard hang issue.
The issue can be solved if we're using the same clock settings as harmony
platform.
And we are not aware that there are devices which are using pll_p_out4 as their
clock source.

Please change back the pll_p_out4 setting if it breaks the ULPI functionality."

I'm unsure how I should test that I'm not breaking the Core DVFS.

[Vincent Palatin, 2011-04-12 17:15:32]

+CC NVidia guys working on clock issues

[Olof Johansson, 2011-04-12 18:17:33]

LGTM

[dahuang, 2011-04-13 11:10:29]

LGTM