Add Tegra2 SPI controller.

internal.c

Index: internal.c
diff --git a/internal.c b/internal.c
index c4e7175cd8aea259b9860caaf7e276eb657a7fb3..fc35b9b604afa84f2c35064c85107eadd68b4214 100644
--- a/internal.c
+++ b/internal.c
@@ -18,8 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
+#include <stdarg.h>
+
 #include "flash.h"
 #include "programmer.h"
 
@@ -116,6 +119,50 @@ void probe_superio(void)
 int is_laptop = 0;
 enum chipbustype target_bus;
 
+#if defined(__i386__) || defined(__x86_64__)
+#define BUFSIZE 256
+static char buffer[BUFSIZE];
+
+static void
+pci_error(char *msg, ...)
+{
+	va_list args;
+
+	va_start(args, msg);
+	vsnprintf(buffer, BUFSIZE, msg, args);
+	va_end(args);
+
+	msg_perr("pcilib: %s\n", buffer);
+
+	/* libpci requires us to exit. TODO cleanup? */
+	exit(1);
+}
+
+static void
+pci_warning(char *msg, ...)
+{
+	va_list args;
+
+	va_start(args, msg);
+	vsnprintf(buffer, BUFSIZE, msg, args);
+	va_end(args);
+
+	msg_pinfo("pcilib: %s\n", buffer);
+}
+
+static void
+pci_debug(char *msg, ...)
+{
+	va_list args;
+
+	va_start(args, msg);
+	vsnprintf(buffer, BUFSIZE, msg, args);
+	va_end(args);
+
+	msg_pdbg("pcilib: %s\n", buffer);
+}
+#endif
+
 int internal_init(void)
 {
 #if __FLASHROM_LITTLE_ENDIAN__
@@ -193,11 +240,17 @@ int internal_init(void)
 
 	get_io_perms();
 
+#if defined(__i386__) || defined(__x86_64__)
 	/* Initialize PCI access for flash enables */
 	pacc = pci_alloc();	/* Get the pci_access structure */
+	pacc->error = pci_error;
+	pacc->warning = pci_warning;
+	pacc->debug = pci_debug;
+
 	/* Set all options you want -- here we stick with the defaults */
 	pci_init(pacc);		/* Initialize the PCI library */
 	pci_scan_bus(pacc);	/* We want to get the list of devices */
+#endif

[Stefan Reinauer, 2011/03/25 16:57:47]

everything up to here in internal.c should be dropped as it has been factored
out into an extra CL

[Louis, 2011/03/29 07:55:02]

Done.

 
 	if (processor_flash_enable()) {
 		msg_perr("Processor detection/init failed.\n"
@@ -224,6 +277,13 @@ int internal_init(void)
 
 	/* Probe for the Super I/O chip and fill global struct superio. */
 	probe_superio();
+
+#elif defined(__arm__)
+	/* We look at the cbtable first to see if we need a
+	 * mainboard specific flash enable sequence.
+	 */
+	coreboot_init();
+
 #else
 	/* FIXME: Enable cbtable searching on all non-x86 platforms supported
 	 *        by coreboot.
@@ -256,6 +316,8 @@ int internal_init(void)
 	}
 
 #if __FLASHROM_LITTLE_ENDIAN__
+
+#if defined(__i386__) || defined(__x86_64__)
 	/* try to enable it. Failure IS an option, since not all motherboards
 	 * really need this to be done, etc., etc.
 	 */
@@ -264,6 +326,7 @@ int internal_init(void)
 		msg_perr("WARNING: No chipset found. Flash detection "
 			 "will most likely fail.\n");
 	}
+#endif
 
 #if defined(__i386__) || defined(__x86_64__)
 	/* Probe unconditionally for IT87* LPC->SPI translation and for
@@ -281,13 +344,18 @@ int internal_init(void)
 
 #endif
 
+#if defined(__i386__) || defined(__x86_64__)
+	msg_perr("Board_flash_enable\n");
+	
 	board_flash_enable(lb_vendor, lb_part);
+#endif
 
 	/* Even if chipset init returns an error code, we don't want to abort.
 	 * The error code might have been a warning only.
 	 * Besides that, we don't check the board enable return code either.
 	 */
-#if defined(__i386__) || defined(__x86_64__) || defined (__mips)
+#if defined(__i386__) || defined(__x86_64__) || defined (__mips) || \
+    defined(__arm__)
 	return 0;
 #else
 	msg_perr("Your platform is not supported yet for the internal "
@@ -321,7 +389,10 @@ int internal_shutdown(void)
 		mec1308_shutdown();
 	}
 #endif
-
+#if defined(__arm__)
+	if (spi_controller == SPI_CONTROLLER_TEGRA2)
+		tegra2_spi_shutdown();
+#endif
 	return 0;
 }
 #endif