Add Tegra2 SPI controller.

internal.c

 /*
  * This file is part of the flashrom project.
  *
  * Copyright (C) 2009 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
+#include <stdarg.h>
+
 #include "flash.h"
 #include "programmer.h"
 
 #if NEED_PCI == 1
 struct pci_dev *pci_dev_find_filter(struct pci_filter filter)
 {
         struct pci_dev *temp;
 
         for (temp = pacc->devices; temp; temp = temp->next)
                 if (pci_filter_match(&filter, temp))
@@ skipping 76 matching lines @@
         /* Winbond Super I/O code is not yet available. */
         if (superio.vendor == SUPERIO_VENDOR_NONE)
                 superio = probe_superio_winbond();
 #endif
 }
 #endif
 
 int is_laptop = 0;
 enum chipbustype target_bus;
 
+#if defined(__i386__) || defined(__x86_64__)
+#define BUFSIZE 256
+static char buffer[BUFSIZE];
+
+static void
+pci_error(char *msg, ...)
+{
+        va_list args;
+
+        va_start(args, msg);
+        vsnprintf(buffer, BUFSIZE, msg, args);
+        va_end(args);
+
+        msg_perr("pcilib: %s\n", buffer);
+
+        /* libpci requires us to exit. TODO cleanup? */
+        exit(1);
+}
+
+static void
+pci_warning(char *msg, ...)
+{
+        va_list args;
+
+        va_start(args, msg);
+        vsnprintf(buffer, BUFSIZE, msg, args);
+        va_end(args);
+
+        msg_pinfo("pcilib: %s\n", buffer);
+}
+
+static void
+pci_debug(char *msg, ...)
+{
+        va_list args;
+
+        va_start(args, msg);
+        vsnprintf(buffer, BUFSIZE, msg, args);
+        va_end(args);
+
+        msg_pdbg("pcilib: %s\n", buffer);
+}
+#endif
+
 int internal_init(void)
 {
 #if __FLASHROM_LITTLE_ENDIAN__
         int ret = 0;
 #endif
         int force_laptop = 0;
         char *arg;
         int probe_target_bus_later = 0;
 
         arg = extract_programmer_param("boardenable");
@@ skipping 57 matching lines @@
                 }
 
                 free(arg);
         } else {
                 /* The pacc must be initialized before access pci devices. */
                 probe_target_bus_later = 1;
         }
 
         get_io_perms();
 
+#if defined(__i386__) || defined(__x86_64__)
         /* Initialize PCI access for flash enables */
         pacc = pci_alloc();     /* Get the pci_access structure */
+        pacc->error = pci_error;
+        pacc->warning = pci_warning;
+        pacc->debug = pci_debug;
+
         /* Set all options you want -- here we stick with the defaults */
         pci_init(pacc);         /* Initialize the PCI library */
         pci_scan_bus(pacc);     /* We want to get the list of devices */
+#endif

[Stefan Reinauer, 2011/03/25 16:57:47]

everything up to here in internal.c should be dropped as it has been factored
out into an extra CL

[Louis, 2011/03/29 07:55:02]

Done.

 
         if (processor_flash_enable()) {
                 msg_perr("Processor detection/init failed.\n"
                          "Aborting.\n");
                 return 1;
         }
 
 #if defined(__i386__) || defined(__x86_64__)
         /* We look at the cbtable first to see if we need a
          * mainboard specific flash enable sequence.
          */
         coreboot_init();
 
         dmi_init();
 
         if (probe_target_bus_later) {
                 /* read the target bus value from register. */
                 if (get_target_bus_from_chipset(&target_bus)) {
                         msg_perr("Cannot get target bus from %s programmer.\n",
                                  programmer_table[programmer].name);
                         return 1;
                 }
         }
 
         /* Probe for the Super I/O chip and fill global struct superio. */
         probe_superio();
+
+#elif defined(__arm__)
+        /* We look at the cbtable first to see if we need a
+         * mainboard specific flash enable sequence.
+         */
+        coreboot_init();
+
 #else
         /* FIXME: Enable cbtable searching on all non-x86 platforms supported
          *        by coreboot.
          * FIXME: Find a replacement for DMI on non-x86.
          * FIXME: Enable Super I/O probing once port I/O is possible.
          */
 #endif
 
         /* Warn if a laptop is detected. */
         if (is_laptop) {
@@ skipping 12 matching lines @@
                 if (force_laptop) {
                         msg_perr("Proceeding anyway because user specified "
                                  "laptop=force_I_want_a_brick\n");
                 } else {
                         msg_perr("Aborting.\n");
                         exit(1);
                 }
         }
 
 #if __FLASHROM_LITTLE_ENDIAN__
+
+#if defined(__i386__) || defined(__x86_64__)
         /* try to enable it. Failure IS an option, since not all motherboards
          * really need this to be done, etc., etc.
          */
         ret = chipset_flash_enable();
         if (ret == -2) {
                 msg_perr("WARNING: No chipset found. Flash detection "
                          "will most likely fail.\n");
         }
+#endif
 
 #if defined(__i386__) || defined(__x86_64__)
         /* Probe unconditionally for IT87* LPC->SPI translation and for
          * IT87* Parallel write enable.
          */
         init_superio_ite();
 
         /* probe for programmers that bridge LPC <--> SPI */
         if (target_bus == CHIP_BUSTYPE_LPC ||
             target_bus == CHIP_BUSTYPE_FWH) {
                 it85xx_probe_spi_flash(NULL);
                 wpce775x_probe_spi_flash(NULL);
                 mec1308_probe_spi_flash(NULL);
         }
 
 #endif
 
+#if defined(__i386__) || defined(__x86_64__)
+        msg_perr("Board_flash_enable\n");
+        
         board_flash_enable(lb_vendor, lb_part);
+#endif
 
         /* Even if chipset init returns an error code, we don't want to abort.
          * The error code might have been a warning only.
          * Besides that, we don't check the board enable return code either.
          */
-#if defined(__i386__) || defined(__x86_64__) || defined (__mips)
+#if defined(__i386__) || defined(__x86_64__) || defined (__mips) || \
+    defined(__arm__)
         return 0;
 #else
         msg_perr("Your platform is not supported yet for the internal "
                  "programmer due to missing\n"
                  "flash_base and top/bottom alignment information.\n"
                  "Aborting.\n");
         return 1;
 #endif
 #else
         /* FIXME: Remove this unconditional abort once all PCI drivers are
@@ skipping 13 matching lines @@
         release_io_perms();
 
 #if defined(__i386__) || defined(__x86_64__)
         if (target_bus == CHIP_BUSTYPE_LPC ||
             target_bus == CHIP_BUSTYPE_FWH) {
                 it85xx_shutdown();
                 wpce775x_shutdown();
                 mec1308_shutdown();
         }
 #endif
-
+#if defined(__arm__)
+        if (spi_controller == SPI_CONTROLLER_TEGRA2)
+                tegra2_spi_shutdown();
+#endif
         return 0;
 }
 #endif
 
 void internal_chip_writeb(uint8_t val, chipaddr addr)
 {
         mmio_writeb(val, (void *) addr);
 }
 
 void internal_chip_writew(uint16_t val, chipaddr addr)
@@ skipping 19 matching lines @@
 uint32_t internal_chip_readl(const chipaddr addr)
 {
         return mmio_readl((void *) addr);
 }
 
 void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len)
 {
         memcpy(buf, (void *)addr, len);
         return;
 }