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Unified Diff: src/arm/codegen-arm.cc

Issue 6696037: Fix incorrect assumption on bit-and on ARM (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 9 years, 9 months ago
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Index: src/arm/codegen-arm.cc
===================================================================
--- src/arm/codegen-arm.cc (revision 7178)
+++ src/arm/codegen-arm.cc (working copy)
@@ -1159,7 +1159,7 @@
}
// Check that the *signed* result fits in a smi. Not necessary for AND, SAR
// if the shift if more than 0 or SHR if the shit is more than 1.
- if (!( (op_ == Token::AND) ||
+ if (!( (op_ == Token::AND && value_ >= 0) ||
((op_ == Token::SAR) && (shift_value > 0)) ||
((op_ == Token::SHR) && (shift_value > 1)))) {
__ add(r3, int32, Operand(0x40000000), SetCC);
@@ -1420,8 +1420,10 @@
default: UNREACHABLE();
}
deferred->BindExit();
- TypeInfo result_type =
- (op == Token::BIT_AND) ? TypeInfo::Smi() : TypeInfo::Integer32();
+ TypeInfo result_type = TypeInfo::Integer32();
+ if (op == Token::BIT_AND && int_value >= 0) {
+ result_type = TypeInfo::Smi();
+ }
frame_->EmitPush(tos, result_type);
}
break;
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