Chromium Code Reviews| Index: include/configs/tegra2_seaboard.h |
| diff --git a/include/configs/tegra2_seaboard.h b/include/configs/tegra2_seaboard.h |
| index 2b4648617678546913e8fdbf5d0262895793d0b9..92d1ebd0494d241c21aa78865db956379bcfccef 100644 |
| --- a/include/configs/tegra2_seaboard.h |
| +++ b/include/configs/tegra2_seaboard.h |
| @@ -165,4 +165,21 @@ |
| 0, 0, 0, 0, 0, 0, 0, 0, \ |
| 0, 0, 0, 0, '?', 0, 0, 0 |
| +/* For HYNIX HY27UF4G2B |
|
Tom Warren
2011/03/17 16:28:49
The NAND BCT CFG files for Seaboard that I've been
|
| + * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz |
| + * to CLK_RST_CONTROLLER_PLLP_BASE_0, |
| + * 216MHz / divisor 4 = 54MHZ |
| + * 1 clock = 18.5 ns = NAND_CLK_PERIOD |
| + * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode |
| + * bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5 |
| + * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24) |
| + * similar way for other fields, please refer to reference manual |
| + */ |
| +/* Value to be set to NAND_TIMING_0 register, address=70008014h */ |
| +#define CONFIG_TEGRA2_NAND_TIMING 0x15040001 |
| +/* Value to be set to NAND_TIMING2_0 register, address=7000801Ch */ |
| +#define CONFIG_TEGRA2_NAND_TIMING2 0x01 |
| +/* tR = Time taken for data transfer from NAND cell to NAND register, |
| + * in micro-second */ |
| +#define CONFIG_TEGRA2_NAND_tR_US 25 |
|
Tom Warren
2011/03/17 16:28:49
Where is this used?
|
| #endif /* __CONFIG_H */ |