Chromium: arm: tegra: Add NAND support

include/configs/tegra2_seaboard.h

 /*
  *  (C) Copyright 2010
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
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+/* For HYNIX HY27UF4G2B

[Tom Warren, 2011/03/17 16:28:49]

The NAND BCT CFG files for Seaboard that I've been able to find all run at
108MHz. Don't we want max speed out of NAND?
This will change the timings here, so the divisor should probably be declared as
a CONFIG option, too.

I'd also like to see these comments/NAND_TIMING #defines in the tegra2_nand.h
header (under an #ifdef CONFIG_TEGRA2_NAND_HYNIX), and something like
CONFIG_TEGRA2_NAND_HYNIX defined here to enable it. Later, if another variant is
built with a different NAND chip (Toshiba, etc.), we just need to define
CONFIG_TEGRA2_NAND_TOSHIBA here, and provide the timings in the NAND driver
header as per the (Toshiba) data sheet.

+ * Frequence output of PLLP_OUT0 is set by BOOTROM to 216MHz
+ * to CLK_RST_CONTROLLER_PLLP_BASE_0,
+ * 216MHz / divisor 4 = 54MHZ
+ * 1 clock = 18.5 ns = NAND_CLK_PERIOD
+ * TRP_RESP_CNT=n, max(tRP, tREA)= max(12ns, 20ns)= 20ns for non-EDO mode
+ *   bit 31-28=n=1, generated timing= (n+1) * NAND_CLK_PERIOD= (1+1)* 18.5
+ * TWB_CNT bit 27-24=n, tWB = 100ns = (n+1)* 18.5, so n= 5 (bit 27-24)
+ * similar way for other fields, please refer to reference manual
+ */
+/* Value to be set to NAND_TIMING_0 register, address=70008014h */
+#define CONFIG_TEGRA2_NAND_TIMING       0x15040001
+/* Value to be set to NAND_TIMING2_0 register, address=7000801Ch */
+#define CONFIG_TEGRA2_NAND_TIMING2      0x01
+/* tR = Time taken for data transfer from NAND cell to NAND register,
+ * in micro-second */
+#define CONFIG_TEGRA2_NAND_tR_US        25

[Tom Warren, 2011/03/17 16:28:49]

Where is this used?

 #endif /* __CONFIG_H */