Fix some style issues in the ARM code....

src/arm/simulator-arm.cc

Index: src/arm/simulator-arm.cc
===================================================================
--- src/arm/simulator-arm.cc	(revision 3292)
+++ src/arm/simulator-arm.cc	(working copy)
@@ -435,9 +435,9 @@
   v_flag_ = false;
 
   // Initializing VFP registers.
-  // All registers are initialized to zero to start with.
+  // All registers are initialized to zero to start with
   // even though s_registers_ & d_registers_ share the same
-  // physical registers in the target
+  // physical registers in the target.
   for (int i = 0; i < num_s_registers; i++) {
     vfp_register[i] = 0;
   }
@@ -567,17 +567,20 @@
   return registers_[pc];
 }
 
+
 // Getting from and setting into VFP registers.
 void Simulator::set_s_register(int sreg, unsigned int value) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   vfp_register[sreg] = value;
 }
 
+
 unsigned int Simulator::get_s_register(int sreg) const {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   return vfp_register[sreg];
 }
 
+
 void Simulator::set_s_register_from_float(int sreg, const float flt) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   // Read the bits from the single precision floating point value
@@ -587,20 +590,22 @@
   memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
 }
 
+
 void Simulator::set_s_register_from_sinteger(int sreg, const int sint) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
-  // Read the bits from the integer value
-  // into the unsigned integer element of vfp_register[] given by index=sreg.
+  // Read the bits from the integer value into the unsigned integer element of
+  // vfp_register[] given by index=sreg.
   char buffer[sizeof(vfp_register[0])];
   memcpy(buffer, &sint, sizeof(vfp_register[0]));
   memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
 }
 
+
 void Simulator::set_d_register_from_double(int dreg, const double& dbl) {
   ASSERT((dreg >= 0) && (dreg < num_d_registers));
-  // Read the bits from the double precision floating point value
-  // into the two consecutive unsigned integer elements of vfp_register[]
-  // given by index 2*sreg and 2*sreg+1.
+  // Read the bits from the double precision floating point value into the two
+  // consecutive unsigned integer elements of vfp_register[] given by index
+  // 2*sreg and 2*sreg+1.
   char buffer[2 * sizeof(vfp_register[0])];
   memcpy(buffer, &dbl, 2 * sizeof(vfp_register[0]));
 #ifndef BIG_ENDIAN_FLOATING_POINT
@@ -611,6 +616,7 @@
 #endif
 }
 
+
 float Simulator::get_float_from_s_register(int sreg) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
 
@@ -623,6 +629,7 @@
   return(sm_val);
 }
 
+
 int Simulator::get_sinteger_from_s_register(int sreg) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
 
@@ -635,6 +642,7 @@
   return(sm_val);
 }
 
+
 double Simulator::get_double_from_d_register(int dreg) {
   ASSERT((dreg >= 0) && (dreg < num_d_registers));
 
@@ -642,11 +650,11 @@
   // Read the bits from the unsigned integer vfp_register[] array
   // into the double precision floating point value and return it.
   char buffer[2 * sizeof(vfp_register[0])];
-#ifndef BIG_ENDIAN_FLOATING_POINT
-  memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0]));
-#else
+#ifdef BIG_ENDIAN_FLOATING_POINT
   memcpy(&buffer[0], &vfp_register[2 * dreg + 1], sizeof(vfp_register[0]));
   memcpy(&buffer[4], &vfp_register[2 * dreg], sizeof(vfp_register[0]));
+#else
+  memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0]));
 #endif
   memcpy(&dm_val, buffer, 2 * sizeof(vfp_register[0]));
   return(dm_val);
@@ -879,9 +887,10 @@
   return overflow;
 }
 
+
 // Support for VFP comparisons.
 void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
-  // All Non-Nan cases
+  // All non-NaN cases.
   if (val1 == val2) {
     n_flag_FPSCR_ = false;
     z_flag_FPSCR_ = true;
@@ -910,7 +919,6 @@
 }
 
 
-
 // Addressing Mode 1 - Data-processing operands:
 // Get the value based on the shifter_operand with register.
 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
@@ -1293,7 +1301,7 @@
           }
         }
       } else {
-        UNIMPLEMENTED();  // not used by V8
+        UNIMPLEMENTED();  // Not used by V8.
       }
     } else {
       // extra load/store instructions
@@ -1952,9 +1960,9 @@
       if (instr->Bits(15, 12) == 0xF)
         Copy_FPSCR_to_APSR();
       else
-        UNIMPLEMENTED();  // not used by V8 now
+        UNIMPLEMENTED();  // Not used by V8.
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   } else if (instr->Bit(21) == 1) {
     if ((instr->Bit(20) == 0x1) &&
@@ -1985,7 +1993,7 @@
       double dd_value = dn_value * dm_value;
       set_d_register_from_double(vd, dd_value);
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   } else {
     if ((instr->Bit(20) == 0x0) &&
@@ -2004,15 +2012,14 @@
                                                        instr->NField()));
       set_register(rt, int_value);
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   }
 }
 
 
-
 // void Simulator::DecodeType6CoprocessorIns(Instr* instr)
-// Decode Type 6 coprocessor instructions
+// Decode Type 6 coprocessor instructions.
 // Dm = fmdrr(Rt, Rt2)
 // <Rt, Rt2> = fmrrd(Dm)
 void Simulator::DecodeType6CoprocessorIns(Instr* instr) {