Fix some style issues in the ARM code....

src/arm/simulator-arm.cc

 // Copyright 2009 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 417 matching lines @@
   // All registers are initialized to zero to start with.
   for (int i = 0; i < num_registers; i++) {
     registers_[i] = 0;
   }
   n_flag_ = false;
   z_flag_ = false;
   c_flag_ = false;
   v_flag_ = false;
 
   // Initializing VFP registers.
-  // All registers are initialized to zero to start with.
+  // All registers are initialized to zero to start with
   // even though s_registers_ & d_registers_ share the same
-  // physical registers in the target
+  // physical registers in the target.
   for (int i = 0; i < num_s_registers; i++) {
     vfp_register[i] = 0;
   }
   n_flag_FPSCR_ = false;
   z_flag_FPSCR_ = false;
   c_flag_FPSCR_ = false;
   v_flag_FPSCR_ = false;
 
   inv_op_vfp_flag_ = false;
   div_zero_vfp_flag_ = false;
@@ skipping 109 matching lines @@
   pc_modified_ = true;
   registers_[pc] = value;
 }
 
 
 // Raw access to the PC register without the special adjustment when reading.
 int32_t Simulator::get_pc() const {
   return registers_[pc];
 }
 
+
 // Getting from and setting into VFP registers.
 void Simulator::set_s_register(int sreg, unsigned int value) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   vfp_register[sreg] = value;
 }
 
+
 unsigned int Simulator::get_s_register(int sreg) const {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   return vfp_register[sreg];
 }
 
+
 void Simulator::set_s_register_from_float(int sreg, const float flt) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
   // Read the bits from the single precision floating point value
   // into the unsigned integer element of vfp_register[] given by index=sreg.
   char buffer[sizeof(vfp_register[0])];
   memcpy(buffer, &flt, sizeof(vfp_register[0]));
   memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
 }
 
+
 void Simulator::set_s_register_from_sinteger(int sreg, const int sint) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
-  // Read the bits from the integer value
-  // into the unsigned integer element of vfp_register[] given by index=sreg.
+  // Read the bits from the integer value into the unsigned integer element of
+  // vfp_register[] given by index=sreg.
   char buffer[sizeof(vfp_register[0])];
   memcpy(buffer, &sint, sizeof(vfp_register[0]));
   memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0]));
 }
 
+
 void Simulator::set_d_register_from_double(int dreg, const double& dbl) {
   ASSERT((dreg >= 0) && (dreg < num_d_registers));
-  // Read the bits from the double precision floating point value
-  // into the two consecutive unsigned integer elements of vfp_register[]
-  // given by index 2*sreg and 2*sreg+1.
+  // Read the bits from the double precision floating point value into the two
+  // consecutive unsigned integer elements of vfp_register[] given by index
+  // 2*sreg and 2*sreg+1.
   char buffer[2 * sizeof(vfp_register[0])];
   memcpy(buffer, &dbl, 2 * sizeof(vfp_register[0]));
 #ifndef BIG_ENDIAN_FLOATING_POINT
   memcpy(&vfp_register[dreg * 2], buffer, 2 * sizeof(vfp_register[0]));
 #else
   memcpy(&vfp_register[dreg * 2], &buffer[4], sizeof(vfp_register[0]));
   memcpy(&vfp_register[dreg * 2 + 1], &buffer[0], sizeof(vfp_register[0]));
 #endif
 }
 
+
 float Simulator::get_float_from_s_register(int sreg) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
 
   float sm_val = 0.0;
   // Read the bits from the unsigned integer vfp_register[] array
   // into the single precision floating point value and return it.
   char buffer[sizeof(vfp_register[0])];
   memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0]));
   memcpy(&sm_val, buffer, sizeof(vfp_register[0]));
   return(sm_val);
 }
 
+
 int Simulator::get_sinteger_from_s_register(int sreg) {
   ASSERT((sreg >= 0) && (sreg < num_s_registers));
 
   int sm_val = 0;
   // Read the bits from the unsigned integer vfp_register[] array
   // into the single precision floating point value and return it.
   char buffer[sizeof(vfp_register[0])];
   memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0]));
   memcpy(&sm_val, buffer, sizeof(vfp_register[0]));
   return(sm_val);
 }
 
+
 double Simulator::get_double_from_d_register(int dreg) {
   ASSERT((dreg >= 0) && (dreg < num_d_registers));
 
   double dm_val = 0.0;
   // Read the bits from the unsigned integer vfp_register[] array
   // into the double precision floating point value and return it.
   char buffer[2 * sizeof(vfp_register[0])];
-#ifndef BIG_ENDIAN_FLOATING_POINT
-  memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0]));
-#else
+#ifdef BIG_ENDIAN_FLOATING_POINT
   memcpy(&buffer[0], &vfp_register[2 * dreg + 1], sizeof(vfp_register[0]));
   memcpy(&buffer[4], &vfp_register[2 * dreg], sizeof(vfp_register[0]));
+#else
+  memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0]));
 #endif
   memcpy(&dm_val, buffer, 2 * sizeof(vfp_register[0]));
   return(dm_val);
 }
 
 
 // For use in calls that take two double values, constructed from r0, r1, r2
 // and r3.
 void Simulator::GetFpArgs(double* x, double* y) {
   // We use a char buffer to get around the strict-aliasing rules which
@@ skipping 212 matching lines @@
                && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
   } else {
                // operands have different signs
     overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
                // and first operand and result have different signs
                && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
   }
   return overflow;
 }
 
+
 // Support for VFP comparisons.
 void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
-  // All Non-Nan cases
+  // All non-NaN cases.
   if (val1 == val2) {
     n_flag_FPSCR_ = false;
     z_flag_FPSCR_ = true;
     c_flag_FPSCR_ = true;
     v_flag_FPSCR_ = false;
   } else if (val1 < val2) {
     n_flag_FPSCR_ = true;
     z_flag_FPSCR_ = false;
     c_flag_FPSCR_ = false;
     v_flag_FPSCR_ = false;
   } else {
     // Case when (val1 > val2).
     n_flag_FPSCR_ = false;
     z_flag_FPSCR_ = false;
     c_flag_FPSCR_ = true;
     v_flag_FPSCR_ = false;
   }
 }
 
 
 void Simulator::Copy_FPSCR_to_APSR() {
   n_flag_ = n_flag_FPSCR_;
   z_flag_ = z_flag_FPSCR_;
   c_flag_ = c_flag_FPSCR_;
   v_flag_ = v_flag_FPSCR_;
 }
 
 
-
 // Addressing Mode 1 - Data-processing operands:
 // Get the value based on the shifter_operand with register.
 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
   Shift shift = instr->ShiftField();
   int shift_amount = instr->ShiftAmountField();
   int32_t result = get_register(instr->RmField());
   if (instr->Bit(4) == 0) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
       UNIMPLEMENTED();
@@ skipping 362 matching lines @@
             hi_res = static_cast<int32_t>(result >> 32);
             lo_res = static_cast<int32_t>(result & 0xffffffff);
           }
           set_register(rd_lo, lo_res);
           set_register(rd_hi, hi_res);
           if (instr->HasS()) {
             UNIMPLEMENTED();
           }
         }
       } else {
-        UNIMPLEMENTED();  // not used by V8
+        UNIMPLEMENTED();  // Not used by V8.
       }
     } else {
       // extra load/store instructions
       int rd = instr->RdField();
       int rn = instr->RnField();
       int32_t rn_val = get_register(rn);
       int32_t addr = 0;
       if (instr->Bit(22) == 0) {
         int rm = instr->RmField();
         int32_t rm_val = get_register(rm);
@@ skipping 638 matching lines @@
       Compute_FPSCR_Flags(dd_value, dm_value);
     } else if ((instr->Bits(23, 20) == 0xF) &&
                (instr->Bits(19, 16) == 0x1) &&
                (instr->Bits(11, 8) == 0xA) &&
                (instr->Bits(7, 5) == 0x0) &&
                (instr->Bit(4) == 0x1)    &&
                (instr->Bits(3, 0) == 0x0)) {
       if (instr->Bits(15, 12) == 0xF)
         Copy_FPSCR_to_APSR();
       else
-        UNIMPLEMENTED();  // not used by V8 now
+        UNIMPLEMENTED();  // Not used by V8.
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   } else if (instr->Bit(21) == 1) {
     if ((instr->Bit(20) == 0x1) &&
         (instr->Bits(11, 9) == 0x5) &&
         (instr->Bit(8) == 0x1) &&
         (instr->Bit(6) == 0) &&
         (instr->Bit(4) == 0)) {
       double dn_value = get_double_from_d_register(vn);
       double dm_value = get_double_from_d_register(vm);
       double dd_value = dn_value + dm_value;
@@ skipping 10 matching lines @@
     } else if ((instr->Bit(20) == 0x0) &&
                (instr->Bits(11, 9) == 0x5) &&
                (instr->Bit(8) == 0x1) &&
                (instr->Bit(6) == 0) &&
                (instr->Bit(4) == 0)) {
       double dn_value = get_double_from_d_register(vn);
       double dm_value = get_double_from_d_register(vm);
       double dd_value = dn_value * dm_value;
       set_d_register_from_double(vd, dd_value);
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   } else {
     if ((instr->Bit(20) == 0x0) &&
         (instr->Bits(11, 8) == 0xA) &&
         (instr->Bits(6, 5) == 0x0) &&
         (instr->Bit(4) == 1) &&
         (instr->Bits(3, 0) == 0x0)) {
       int32_t rs_val = get_register(rt);
       set_s_register_from_sinteger(((vn<<1) | instr->NField()), rs_val);
     } else if ((instr->Bit(20) == 0x1) &&
                (instr->Bits(11, 8) == 0xA) &&
                (instr->Bits(6, 5) == 0x0) &&
                (instr->Bit(4) == 1) &&
                (instr->Bits(3, 0) == 0x0)) {
       int32_t int_value = get_sinteger_from_s_register(((vn<<1) |
                                                        instr->NField()));
       set_register(rt, int_value);
     } else {
-      UNIMPLEMENTED();  // not used by V8 now
+      UNIMPLEMENTED();  // Not used by V8.
     }
   }
 }
 
 
-
 // void Simulator::DecodeType6CoprocessorIns(Instr* instr)
-// Decode Type 6 coprocessor instructions
+// Decode Type 6 coprocessor instructions.
 // Dm = fmdrr(Rt, Rt2)
 // <Rt, Rt2> = fmrrd(Dm)
 void Simulator::DecodeType6CoprocessorIns(Instr* instr) {
   ASSERT((instr->TypeField() == 6));
 
   int rt = instr->RtField();
   int rn = instr->RnField();
   int vm = instr->VmField();
 
   if (instr->Bit(23) == 1) {
@@ skipping 222 matching lines @@
   uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
   uintptr_t address = *stack_slot;
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 
 } }  // namespace assembler::arm
 
 #endif  // !defined(__arm__)