X64: Added implementations of Set(..., Immediate) to macro assembler.

src/x64/assembler-x64.h

Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index 170e6d67572471ddb7e198e1be1ad0420b2b21f3..c1ba236a58785821c873091930f9c3a2d2624dfa 100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -40,6 +40,19 @@
 namespace v8 {
 namespace internal {
 
+// Utility functions
+
+// Test whether a 64-bit value is in a specific range.
+static inline bool is_uint32(int64_t x) {
+  static const unsigned int kUInt32Mask = 0xffffffff;

[William Hesse, 2009/06/02 13:21:58]

Please use the V8_UINT64_C() macro to define a 64-bit mask.  Relying on the fact
that it gets extended to 64 bits from an unsigned is confusing.

In fact, for consistency, copy the is_intn and is_uintn functions from
assembler.h, using 64-bit types.  Either instantiate is_uint32 directly, or
rename is_uintn to is_uint64n, since you can't overload on integer type
reliably, I think.

+  return x == x & kUInt32Mask;
+}
+
+static inline bool is_int32(int64_t x) {
+  static const int kMinIntValue = -0x80000000;
+  return is_uint32(x - kMinIntValue);
+}
+
 // CPU Registers.
 //
 // 1) We would prefer to use an enum, but enum values are assignment-
@@ -409,11 +422,15 @@ class Assembler : public Malloced {
   void movb(const Operand& dst, int8_t imm8);
   void movb(const Operand& dst, Register src);
 
-  void movq(Register dst, int32_t imm32);
-  void movq(Register dst, Immediate x);
+  // Load a 32-bit immediate value, zero-extended to 64 bits.
+  void movl(Register dst, Immediate imm32);
+
   void movq(Register dst, const Operand& src);
+  // Sign extends immediate 32-bit value to 64 bits.
+  void movq(Register dst, Immediate x);
   void movq(Register dst, Register src);
-  void movq(const Operand& dst, const Immediate& x);
+
+  // Move 64 bit register value to 64-bit memory location.
   void movq(const Operand& dst, Register src);
 
   // New x64 instructions to load a 64-bit immediate into a register.
@@ -424,6 +441,7 @@ class Assembler : public Malloced {
   void movq(Register dst, const ExternalReference& ext, RelocInfo::Mode rmode);
   void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
 
+
   // New x64 instruction to load from an immediate 64-bit pointer into RAX.
   void load_rax(void* ptr, RelocInfo::Mode rmode);
 
@@ -850,6 +868,14 @@ class Assembler : public Malloced {
   // is used for REX.X.  REX.W is cleared.
   inline void emit_rex_32(Register reg, const Operand& op);
 
+  // High bit of rm_reg goes to REX.B.
+  // REX.W, REX.R and REX.X are clear.
+  inline void emit_rex_32(Register rm_reg);
+
+  // High bit of base goes to REX.B and high bit of index to REX.X.
+  // REX.W and REX.R are clear.
+  inline void emit_rex_32(const Operand &);

[William Hesse, 2009/06/03 10:36:09]

Operand&, not Operand &

+
   // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
   // REX.W is cleared.  If no REX bits are set, no byte is emitted.
   inline void emit_optional_rex_32(Register reg, Register rm_reg);
@@ -860,6 +886,15 @@ class Assembler : public Malloced {
   // is emitted.
   inline void emit_optional_rex_32(Register reg, const Operand& op);
 
+  // Optionally do as emit_rex_32(Register) if the register number has
+  // the high bit set.
+  inline void emit_optional_rex_32(Register rm_reg);
+
+  // Optionally do as emit_rex_32(const Operand&) if the operand register
+  // numbers have a high bit set.
+  inline void emit_optional_rex_32(const Operand& op);
+
+
   // Emit the Mod/RM byte, and optionally the SIB byte and
   // 1- or 4-byte offset for a memory operand.  Also encodes
   // the second operand of the operation, a register or operation