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Unified Diff: src/trusted/validator_ragel/unreviewed/parse_instruction.rl

Issue 11000033: Move validator_x86_XX.rl out of unreviewed. (Closed) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client/
Patch Set: Created 8 years, 2 months ago
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Index: src/trusted/validator_ragel/unreviewed/parse_instruction.rl
===================================================================
--- src/trusted/validator_ragel/unreviewed/parse_instruction.rl (revision 9911)
+++ src/trusted/validator_ragel/unreviewed/parse_instruction.rl (working copy)
@@ -174,71 +174,71 @@
action operands_count_is_4 { SET_OPERANDS_COUNT(4); }
action operands_count_is_5 { SET_OPERANDS_COUNT(5); }
- action operand0_16bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_16_BIT); }
- action operand0_8bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_8_BIT); }
- action operand0_32bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_32_BIT); }
- action operand0_64bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_64_BIT); }
- action operand0_128bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_128_BIT); }
- action operand0_256bit { SET_OPERAND_TYPE(0, OPERAND_SIZE_256_BIT); }
- action operand0_creg { SET_OPERAND_TYPE(0, OPERAND_CONTROL_REGISTER); }
- action operand0_dreg { SET_OPERAND_TYPE(0, OPERAND_DEBUG_REGISTER); }
- action operand0_farptr { SET_OPERAND_TYPE(0, OPERAND_FAR_PTR); }
- action operand0_float32bit { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_32_BIT); }
- action operand0_float64bit { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_64_BIT); }
- action operand0_float80bit { SET_OPERAND_TYPE(0, OPERAND_FLOAT_SIZE_80_BIT); }
- action operand0_mmx { SET_OPERAND_TYPE(0, OPERAND_MMX); }
- action operand0_segreg { SET_OPERAND_TYPE(0, OPERAND_SEGMENT_REGISTER); }
- action operand0_selector { SET_OPERAND_TYPE(0, OPERAND_SELECTOR); }
- action operand0_x87 { SET_OPERAND_TYPE(0, OPERAND_ST); }
- action operand0_x87_16bit { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_16_BIT); }
- action operand0_x87_32bit { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_32_BIT); }
- action operand0_x87_64bit { SET_OPERAND_TYPE(0, OPERAND_X87_SIZE_64_BIT); }
- action operand0_x87_bcd { SET_OPERAND_TYPE(0, OPERAND_X87_BCD); }
- action operand0_x87_env { SET_OPERAND_TYPE(0, OPERAND_X87_ENV); }
+ action operand0_16bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_16_BIT); }
+ action operand0_8bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_8_BIT); }
+ action operand0_32bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_32_BIT); }
+ action operand0_64bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_64_BIT); }
+ action operand0_128bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_128_BIT); }
+ action operand0_256bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_256_BIT); }
+ action operand0_creg { SET_OPERAND_TYPE(0, OPERAND_TYPE_CONTROL_REGISTER); }
+ action operand0_dreg { SET_OPERAND_TYPE(0, OPERAND_TYPE_DEBUG_REGISTER); }
+ action operand0_farptr { SET_OPERAND_TYPE(0, OPERAND_TYPE_FAR_PTR); }
+ action operand0_float32bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_32_BIT); }
+ action operand0_float64bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_64_BIT); }
+ action operand0_float80bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_FLOAT_80_BIT); }
+ action operand0_mmx { SET_OPERAND_TYPE(0, OPERAND_TYPE_MMX); }
+ action operand0_segreg { SET_OPERAND_TYPE(0, OPERAND_TYPE_SEGMENT_REGISTER); }
+ action operand0_selector { SET_OPERAND_TYPE(0, OPERAND_TYPE_SELECTOR); }
+ action operand0_x87 { SET_OPERAND_TYPE(0, OPERAND_TYPE_ST); }
+ action operand0_x87_16bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_16_BIT); }
+ action operand0_x87_32bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_32_BIT); }
+ action operand0_x87_64bit { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_64_BIT); }
+ action operand0_x87_bcd { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_BCD); }
+ action operand0_x87_env { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_ENV); }
action operand0_x87_mmx_xmm_state {
- SET_OPERAND_TYPE(0, OPERAND_X87_MMX_MM_STATE);
+ SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_MMX_XMM_STATE);
}
- action operand0_x87_state { SET_OPERAND_TYPE(0, OPERAND_X87_STATE); }
- action operand0_xmm { SET_OPERAND_TYPE(0, OPERAND_XMM); }
- action operand0_ymm { SET_OPERAND_TYPE(0, OPERAND_YMM); }
+ action operand0_x87_state { SET_OPERAND_TYPE(0, OPERAND_TYPE_X87_STATE); }
+ action operand0_xmm { SET_OPERAND_TYPE(0, OPERAND_TYPE_XMM); }
+ action operand0_ymm { SET_OPERAND_TYPE(0, OPERAND_TYPE_YMM); }
- action operand1_8bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_8_BIT); }
- action operand1_16bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_16_BIT); }
- action operand1_32bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_32_BIT); }
- action operand1_64bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_64_BIT); }
- action operand1_128bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_128_BIT); }
- action operand1_256bit { SET_OPERAND_TYPE(1, OPERAND_SIZE_256_BIT); }
- action operand1_creg { SET_OPERAND_TYPE(1, OPERAND_CONTROL_REGISTER); }
- action operand1_dreg { SET_OPERAND_TYPE(1, OPERAND_DEBUG_REGISTER); }
- action operand1_farptr { SET_OPERAND_TYPE(1, OPERAND_FAR_PTR); }
- action operand1_float32bit { SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_32_BIT); }
- action operand1_float64bit { SET_OPERAND_TYPE(1, OPERAND_FLOAT_SIZE_64_BIT); }
- action operand1_mmx { SET_OPERAND_TYPE(1, OPERAND_MMX); }
- action operand1_segreg { SET_OPERAND_TYPE(1, OPERAND_SEGMENT_REGISTER); }
- action operand1_x87 { SET_OPERAND_TYPE(1, OPERAND_ST); }
- action operand1_xmm { SET_OPERAND_TYPE(1, OPERAND_XMM); }
- action operand1_ymm { SET_OPERAND_TYPE(1, OPERAND_YMM); }
+ action operand1_8bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_8_BIT); }
+ action operand1_16bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_16_BIT); }
+ action operand1_32bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_32_BIT); }
+ action operand1_64bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_64_BIT); }
+ action operand1_128bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_128_BIT); }
+ action operand1_256bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_256_BIT); }
+ action operand1_creg { SET_OPERAND_TYPE(1, OPERAND_TYPE_CONTROL_REGISTER); }
+ action operand1_dreg { SET_OPERAND_TYPE(1, OPERAND_TYPE_DEBUG_REGISTER); }
+ action operand1_farptr { SET_OPERAND_TYPE(1, OPERAND_TYPE_FAR_PTR); }
+ action operand1_float32bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_32_BIT); }
+ action operand1_float64bit { SET_OPERAND_TYPE(1, OPERAND_TYPE_FLOAT_64_BIT); }
+ action operand1_mmx { SET_OPERAND_TYPE(1, OPERAND_TYPE_MMX); }
+ action operand1_segreg { SET_OPERAND_TYPE(1, OPERAND_TYPE_SEGMENT_REGISTER); }
+ action operand1_x87 { SET_OPERAND_TYPE(1, OPERAND_TYPE_ST); }
+ action operand1_xmm { SET_OPERAND_TYPE(1, OPERAND_TYPE_XMM); }
+ action operand1_ymm { SET_OPERAND_TYPE(1, OPERAND_TYPE_YMM); }
- action operand2_8bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_8_BIT); }
- action operand2_16bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_16_BIT); }
- action operand2_32bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_32_BIT); }
- action operand2_64bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_64_BIT); }
- action operand2_128bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_128_BIT); }
- action operand2_256bit { SET_OPERAND_TYPE(2, OPERAND_SIZE_256_BIT); }
- action operand2_float32bit { SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_32_BIT); }
- action operand2_float64bit { SET_OPERAND_TYPE(2, OPERAND_FLOAT_SIZE_64_BIT); }
- action operand2_xmm { SET_OPERAND_TYPE(2, OPERAND_XMM); }
- action operand2_ymm { SET_OPERAND_TYPE(2, OPERAND_YMM); }
+ action operand2_8bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_8_BIT); }
+ action operand2_16bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_16_BIT); }
+ action operand2_32bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_32_BIT); }
+ action operand2_64bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_64_BIT); }
+ action operand2_128bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_128_BIT); }
+ action operand2_256bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_256_BIT); }
+ action operand2_float32bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_32_BIT); }
+ action operand2_float64bit { SET_OPERAND_TYPE(2, OPERAND_TYPE_FLOAT_64_BIT); }
+ action operand2_xmm { SET_OPERAND_TYPE(2, OPERAND_TYPE_XMM); }
+ action operand2_ymm { SET_OPERAND_TYPE(2, OPERAND_TYPE_YMM); }
- action operand3_8bit { SET_OPERAND_TYPE(3, OPERAND_SIZE_8_BIT); }
- action operand3_128bit { SET_OPERAND_TYPE(3, OPERAND_SIZE_128_BIT); }
- action operand3_256bit { SET_OPERAND_TYPE(3, OPERAND_SIZE_256_BIT); }
- action operand3_float32bit { SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_32_BIT); }
- action operand3_float64bit { SET_OPERAND_TYPE(3, OPERAND_FLOAT_SIZE_64_BIT); }
- action operand3_xmm { SET_OPERAND_TYPE(3, OPERAND_XMM); }
- action operand3_ymm { SET_OPERAND_TYPE(3, OPERAND_YMM); }
+ action operand3_8bit { SET_OPERAND_TYPE(3, OPERAND_TYPE_8_BIT); }
+ action operand3_128bit { SET_OPERAND_TYPE(3, OPERAND_TYPE_128_BIT); }
+ action operand3_256bit { SET_OPERAND_TYPE(3, OPERAND_TYPE_256_BIT); }
+ action operand3_float32bit { SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_32_BIT); }
+ action operand3_float64bit { SET_OPERAND_TYPE(3, OPERAND_TYPE_FLOAT_64_BIT); }
+ action operand3_xmm { SET_OPERAND_TYPE(3, OPERAND_TYPE_XMM); }
+ action operand3_ymm { SET_OPERAND_TYPE(3, OPERAND_TYPE_YMM); }
- action operand4_2bit { SET_OPERAND_TYPE(4, OPERAND_SIZE_2_BIT); }
+ action operand4_2bit { SET_OPERAND_TYPE(4, OPERAND_TYPE_2_BIT); }
action operand0_ds_rbx { SET_OPERAND_NAME(0, REG_DS_RBX); }
action operand0_ds_rsi { SET_OPERAND_NAME(0, REG_DS_RSI); }
@@ -302,9 +302,9 @@
include operand_actions_common
"native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
- action operand0_regsize { SET_OPERAND_TYPE(0, OPERAND_SIZE_32_BIT); }
- action operand1_regsize { SET_OPERAND_TYPE(1, OPERAND_SIZE_32_BIT); }
- action operand2_regsize { SET_OPERAND_TYPE(2, OPERAND_SIZE_32_BIT); }
+ action operand0_regsize { SET_OPERAND_TYPE(0, OPERAND_TYPE_32_BIT); }
+ action operand1_regsize { SET_OPERAND_TYPE(1, OPERAND_TYPE_32_BIT); }
+ action operand2_regsize { SET_OPERAND_TYPE(2, OPERAND_TYPE_32_BIT); }
action operand0_absolute_disp {
SET_OPERAND_NAME(0, REG_RM);
@@ -362,9 +362,9 @@
include operand_actions_common
"native_client/src/trusted/validator_ragel/unreviewed/parse_instruction.rl";
- action operand0_regsize { SET_OPERAND_TYPE(0, OPERAND_SIZE_64_BIT); }
- action operand1_regsize { SET_OPERAND_TYPE(1, OPERAND_SIZE_64_BIT); }
- action operand2_regsize { SET_OPERAND_TYPE(2, OPERAND_SIZE_64_BIT); }
+ action operand0_regsize { SET_OPERAND_TYPE(0, OPERAND_TYPE_64_BIT); }
+ action operand1_regsize { SET_OPERAND_TYPE(1, OPERAND_TYPE_64_BIT); }
+ action operand2_regsize { SET_OPERAND_TYPE(2, OPERAND_TYPE_64_BIT); }
action operand0_absolute_disp {
SET_OPERAND_NAME(0, REG_RM);
@@ -885,3 +885,31 @@
rel16 = any{2} @~rel16_operand_begin @rel16_operand_end;
rel32 = any{4} @~rel32_operand_begin @rel32_operand_end;
}%%
+
+%%{
+ machine decoder;
+
+ decoder = (one_instruction
+ @{
+ process_instruction(instruction_start, current_position+1, &instruction,
+ userdata);
+ instruction_start = current_position + 1;
+ SET_DISP_TYPE(DISPNONE);
+ SET_IMM_TYPE(IMMNONE);
+ SET_IMM2_TYPE(IMMNONE);
+ SET_REX_PREFIX(FALSE);
+ SET_DATA16_PREFIX(FALSE);
+ SET_LOCK_PREFIX(FALSE);
+ SET_REPNZ_PREFIX(FALSE);
+ SET_REPZ_PREFIX(FALSE);
+ SET_BRANCH_NOT_TAKEN(FALSE);
+ SET_BRANCH_TAKEN(FALSE);
+ /* Top three bis of VEX2 are inverted: see AMD/Intel manual. */
+ SET_VEX_PREFIX2(0xe0);
+ SET_VEX_PREFIX3(0x00);
+ })*
+ $!{ process_error(current_position, userdata);
+ result = FALSE;
+ goto error_detected;
+ };
+}%%

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