Support for SDIV and MLS ARM instructions, and implement DoModI using them

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
===================================================================
--- src/arm/disasm-arm.cc	(revision 12559)
+++ src/arm/disasm-arm.cc	(working copy)
@@ -692,11 +692,19 @@
             // Rn field to encode it.
             Format(instr, "mul'cond's 'rn, 'rm, 'rs");
           } else {
-            // The MLA instruction description (A 4.1.28) refers to the order
-            // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
-            // Rn field to encode the Rd register and the Rd field to encode
-            // the Rn register.
-            Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
+            if (instr->Bit(22) == 0) {
+              // The MLA instruction description (A 4.1.28) refers to the order
+              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
+              // Rn field to encode the Rd register and the Rd field to encode
+              // the Rn register.
+              Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
+            } else {
+              // The MLS instruction description (A 4.1.29) refers to the order
+              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
+              // Rn field to encode the Rd register and the Rd field to encode
+              // the Rn register.
+              Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
+            }
           }
         } else {
           // The signed/long multiply instructions use the terms RdHi and RdLo
@@ -974,6 +982,17 @@
       break;
     }
     case db_x: {
+#if CAN_USE_INTEGER_DIVISION

[danno, 2012/09/27 15:28:09]

Need to be a runtime check rather than a compile-time check, introduced in the
same way as VFP3 support works. 

+      if (!instr->HasW()) {
+        if (instr->Bits(5, 4) == 0x1) {
+           if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
+             // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
+             Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
+             break;
+           }
+        }
+      }
+#endif
       Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
       break;
     }