Support for SDIV and MLS ARM instructions, and implement DoModI using them

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 674 matching lines @@
     if (instr->Bits(7, 4) == 9) {
       if (instr->Bit(24) == 0) {
         // multiply instructions
         if (instr->Bit(23) == 0) {
           if (instr->Bit(21) == 0) {
             // The MUL instruction description (A 4.1.33) refers to Rd as being
             // the destination for the operation, but it confusingly uses the
             // Rn field to encode it.
             Format(instr, "mul'cond's 'rn, 'rm, 'rs");
           } else {
-            // The MLA instruction description (A 4.1.28) refers to the order
-            // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
-            // Rn field to encode the Rd register and the Rd field to encode
-            // the Rn register.
-            Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
+            if (instr->Bit(22) == 0) {
+              // The MLA instruction description (A 4.1.28) refers to the order
+              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
+              // Rn field to encode the Rd register and the Rd field to encode
+              // the Rn register.
+              Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
+            } else {
+              // The MLS instruction description (A 4.1.29) refers to the order
+              // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
+              // Rn field to encode the Rd register and the Rd field to encode
+              // the Rn register.
+              Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
+            }
           }
         } else {
           // The signed/long multiply instructions use the terms RdHi and RdLo
           // when referring to the target registers. They are mapped to the Rn
           // and Rd fields as follows:
           // RdLo == Rd field
           // RdHi == Rn field
           // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
           Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
         }
@@ skipping 257 matching lines @@
           Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
         } else {
           UNREACHABLE();  // SSAT.
         }
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
       }
       break;
     }
     case db_x: {
+#if CAN_USE_INTEGER_DIVISION

[danno, 2012/09/27 15:28:09]

Need to be a runtime check rather than a compile-time check, introduced in the
same way as VFP3 support works. 

+      if (!instr->HasW()) {
+        if (instr->Bits(5, 4) == 0x1) {
+           if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
+             // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
+             Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
+             break;
+           }
+        }
+      }
+#endif
       Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
       break;
     }
     case ib_x: {
       if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
         uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
         uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
         uint32_t msbit = widthminus1 + lsbit;
         if (msbit <= 31) {
           if (instr->Bit(22)) {
@@ skipping 520 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM