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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1200 | 1200 |
1201 // Multiply instructions. | 1201 // Multiply instructions. |
1202 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, | 1202 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA, |
1203 SBit s, Condition cond) { | 1203 SBit s, Condition cond) { |
1204 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); | 1204 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
1205 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | | 1205 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 | |
1206 src2.code()*B8 | B7 | B4 | src1.code()); | 1206 src2.code()*B8 | B7 | B4 | src1.code()); |
1207 } | 1207 } |
1208 | 1208 |
1209 | 1209 |
| 1210 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA, |
| 1211 Condition cond) { |
| 1212 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
| 1213 emit(cond | B22 | B21 | dst.code()*B16 | srcA.code()*B12 | |
| 1214 src2.code()*B8 | B7 | B4 | src1.code()); |
| 1215 } |
| 1216 |
| 1217 |
| 1218 void Assembler::sdiv(Register dst, Register src1, Register src2, |
| 1219 Condition cond) { |
| 1220 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
| 1221 emit(cond | B26 | B25| B24 | B20 | dst.code()*B16 | 0xf * B12 | |
| 1222 src2.code()*B8 | B4 | src1.code()); |
| 1223 } |
| 1224 |
| 1225 |
1210 void Assembler::mul(Register dst, Register src1, Register src2, | 1226 void Assembler::mul(Register dst, Register src1, Register src2, |
1211 SBit s, Condition cond) { | 1227 SBit s, Condition cond) { |
1212 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); | 1228 ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
1213 // dst goes in bits 16-19 for this instruction! | 1229 // dst goes in bits 16-19 for this instruction! |
1214 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); | 1230 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
1215 } | 1231 } |
1216 | 1232 |
1217 | 1233 |
1218 void Assembler::smlal(Register dstL, | 1234 void Assembler::smlal(Register dstL, |
1219 Register dstH, | 1235 Register dstH, |
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2688 | 2704 |
2689 // Since a constant pool was just emitted, move the check offset forward by | 2705 // Since a constant pool was just emitted, move the check offset forward by |
2690 // the standard interval. | 2706 // the standard interval. |
2691 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 2707 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
2692 } | 2708 } |
2693 | 2709 |
2694 | 2710 |
2695 } } // namespace v8::internal | 2711 } } // namespace v8::internal |
2696 | 2712 |
2697 #endif // V8_TARGET_ARCH_ARM | 2713 #endif // V8_TARGET_ARCH_ARM |
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