Support for unboxed 64-bit integer bitwise operations and equality on ia32.

runtime/vm/assembler_ia32_test.cc

Index: runtime/vm/assembler_ia32_test.cc
===================================================================
--- runtime/vm/assembler_ia32_test.cc	(revision 12897)
+++ runtime/vm/assembler_ia32_test.cc	(working copy)
@@ -1655,6 +1655,48 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(Orpd, assembler) {

[srdjan, 2012/09/28 16:50:26]

Disable appropriate tests if SSE4_1 not supported

[Florian Schneider, 2012/10/02 11:10:31]

I added tests for the 4.1 specific instructions. Those were not tested yet.

+  __ movsd(XMM0, Address(ESP, kWordSize));
+  __ xorpd(XMM1, XMM1);
+  __ DoubleNegate(XMM1);
+  __ orpd(XMM0, XMM1);
+  __ pushl(EAX);
+  __ pushl(EAX);
+  __ movsd(Address(ESP, 0), XMM0);
+  __ fldl(Address(ESP, 0));
+  __ popl(EAX);
+  __ popl(EAX);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(Orpd, entry) {
+  typedef double (*OrpdCode)(double d);
+  double res = reinterpret_cast<OrpdCode>(entry)(12.56e3);
+  EXPECT_FLOAT_EQ(-12.56e3, res, 0.0);
+}
+
+
+ASSEMBLER_TEST_GENERATE(AndPd, assembler) {
+  __ movsd(XMM0, Address(ESP, kWordSize));
+  __ andpd(XMM0, XMM0);
+  __ pushl(EAX);
+  __ pushl(EAX);
+  __ movsd(Address(ESP, 0), XMM0);
+  __ fldl(Address(ESP, 0));
+  __ popl(EAX);
+  __ popl(EAX);
+  __ ret();
+}
+
+
+ASSEMBLER_TEST_RUN(AndPd, entry) {
+  typedef double (*AndpdCode)(double d);
+  double res = reinterpret_cast<AndpdCode>(entry)(12.56e3);
+  EXPECT_FLOAT_EQ(12.56e3, res, 0.0);
+}
+
+
 ASSEMBLER_TEST_GENERATE(DoubleAbs, assembler) {
   __ movsd(XMM0, Address(ESP, kWordSize));
   __ DoubleAbs(XMM0);