Support for unboxed 64-bit integer bitwise operations and equality on ia32.

runtime/vm/assembler_ia32.cc

Index: runtime/vm/assembler_ia32.cc
===================================================================
--- runtime/vm/assembler_ia32.cc	(revision 12897)
+++ runtime/vm/assembler_ia32.cc	(working copy)
@@ -701,6 +701,15 @@
 }
 
 
+void Assembler::orpd(XmmRegister dst, XmmRegister src) {

[srdjan, 2012/09/28 16:50:26]

Please add asserts at SSE4_1 only instructions.

[Florian Schneider, 2012/10/02 11:10:31]

Done.

+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x66);
+  EmitUint8(0x0F);
+  EmitUint8(0x56);
+  EmitXmmRegisterOperand(dst, src);
+}
+
+
 void Assembler::xorps(XmmRegister dst, const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
@@ -726,6 +735,47 @@
 }
 
 
+void Assembler::andpd(XmmRegister dst, XmmRegister src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x66);
+  EmitUint8(0x0F);
+  EmitUint8(0x54);
+  EmitXmmRegisterOperand(dst, src);
+}
+
+
+void Assembler::pextrd(Register dst, XmmRegister src, const Immediate& imm) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x66);
+  EmitUint8(0x0F);
+  EmitUint8(0x3A);
+  EmitUint8(0x16);
+  EmitOperand(src, Operand(dst));
+  ASSERT(imm.is_uint8());
+  EmitUint8(imm.value());
+}
+
+
+void Assembler::pmovsxdq(XmmRegister dst, XmmRegister src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x66);
+  EmitUint8(0x0F);
+  EmitUint8(0x38);
+  EmitUint8(0x25);
+  EmitXmmRegisterOperand(dst, src);
+}
+
+
+void Assembler::pcmpeqq(XmmRegister dst, XmmRegister src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitUint8(0x66);
+  EmitUint8(0x0F);
+  EmitUint8(0x38);
+  EmitUint8(0x29);
+  EmitXmmRegisterOperand(dst, src);
+}
+
+
 void Assembler::fldl(const Address& src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0xDD);