[MIPS] Implementation of sel_ldr for MIPS architecture.

src/trusted/service_runtime/arch/mips/sel_ldr_mips.h

+/*
+ * Copyright 2012 The Native Client Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can
+ * be found in the LICENSE file.
+ */
+
+#ifndef SERVICE_RUNTIME_ARCH_MIPS_SEL_LDR_H__
+#define SERVICE_RUNTIME_ARCH_MIPS_SEL_LDR_H__ 1
+
+#include "native_client/src/include/portability.h"
+#include "native_client/src/trusted/service_runtime/nacl_config.h"
+
+#define NACL_MAX_ADDR_BITS      30
+
+#define NACL_ADDRSPACE_LOWER_GUARD_SIZE 0
+#define NACL_ADDRSPACE_UPPER_GUARD_SIZE 0x2000
+
+/* Must be synced with irt_compatible_rodata_addr in SConstruct */
+#define NACL_DATA_SEGMENT_START 0x10000000
+
+#define NACL_THREAD_MAX         8192
+
+#define NACL_NOOP_OPCODE        0x00000000  /* nop */
+#define NACL_HALT_OPCODE        0x00000008  /* jr $0 */

[Mark Seaborn, 2012/09/18 03:24:34]

I'm not sure if this was addressed by your design document, but does a delay
slot get executed after the "jr $0" instruction, and if so, is it safe?

(No change required here, just curious.)

[petarj, 2012/09/19 17:27:51]

It gets executed, but the exception occurs right after, so it can not do any
damage.

[Mark Seaborn, 2012/09/20 02:40:42]

Did you consider using a breakpoint instruction?  Would that avoid a delay slot?
 We use a breakpoint instruction on ARM.

[petarj, 2012/09/20 15:33:00]

We hesitated previously to use break instruction, 'jr $0' seemed more
appropriate.
Yes, that would avoid delay slot. Will try that and include it as a separate CL
after testing.

+#define NACL_HALT_LEN           4           /* length of halt instruction */
+#define NACL_HALT_WORD          NACL_HALT_OPCODE
+
+struct NaClApp;

[Mark Seaborn, 2012/09/18 03:24:34]

Nit: you don't need these two forward declarations here

[petarj, 2012/09/19 17:27:51]

Done.

+struct NaClThreadContext;
+
+#endif /* SERVICE_RUNTIME_ARCH_MIPS_SEL_LDR_H__ */