[MIPS] Implementation of sel_ldr for MIPS architecture.

src/include/linux/mips/atomic_ops.h

+/*
+ * Copyright (c) 2012 The Native Client Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef NATIVE_CLIENT_SRC_INCLUDE_LINUX_MIPS_ATOMIC_OPS_LINUX_MIPS_H_
+#define NATIVE_CLIENT_SRC_INCLUDE_LINUX_MIPS_ATOMIC_OPS_LINUX_MIPS_H_ 1
+
+// Used only by trusted code.  Untrusted code uses gcc intrinsics.

[Mark Seaborn, 2012/09/08 02:43:14]

Please use C /* ... */ comments in C (even if copying this file from the ARM
version :-) ).

[petarj, 2012/09/11 16:58:13]

Done.

+
+#include "native_client/src/include/portability.h"
+#include <stdint.h>
+
+typedef int32_t Atomic32;
+
+static INLINE Atomic32 CompareAndSwap(volatile Atomic32* ptr,
+                                      Atomic32 old_value,
+                                      Atomic32 new_value) {
+  Atomic32 ret;
+
+  __asm__ __volatile__("1:\n"

[Mark Seaborn, 2012/09/08 02:43:14]

You should really just use the GCC intrinsics for this.  I don't think there is
any reason to write assembly here.

The same goes for linux/{arm,x86}/atomic_ops.h -- would you like to do a
separate cleanup change to switch these to use GCC intrinsics?

[petarj, 2012/09/11 16:58:13]

I suggest that we do a separate cleanup change for this. I can open a ticket for
it so we do not forget it, if you want.

[Mark Seaborn, 2012/09/13 19:44:36]

Would you mind doing the separate cleanup change as a first step?  That's what
we did when a similar issue came up with Chromium's atomic ops code when we
needed ARM support (in
https://src.chromium.org/viewvc/chrome?view=rev&revision=152791).

[petarj, 2012/09/14 23:14:48]

Is this one what you had in mind:

http://codereview.chromium.org/10913285/ ?

+                       "ll %0, %1\n"  // ret = *ptr
+                       "bne %0, %3, 2f\n"  // if (ret != old_value) goto 2
+                       "nop\n"  // delay slot nop
+                       "sc %2, %1\n"  // *ptr = new_value (with atomic check)
+                       "beqz %2, 1b\n"  // start again on atomic error
+                       "nop\n"  // delay slot nop
+                       "2:\n"
+                       : "=&r" (ret), "=m" (*ptr), "+&r" (new_value)
+                       : "Ir" (old_value), "r" (new_value), "m" (*ptr)
+                       : "memory");
+
+
+  return ret;
+}
+
+static INLINE Atomic32 AtomicExchange(volatile Atomic32* ptr,
+                                      Atomic32 new_value) {
+  Atomic32 tmp, old;
+
+  __asm__ __volatile__("1:\n"
+                       "ll %1, %2\n"  // old = *ptr
+                       "move %0, %3\n"  // tmp = new_value
+                       "sc %0, %2\n"  // *ptr = tmp (with atomic check)
+                       "beqz %0, 1b\n"  // start again on atomic error
+                       "nop\n"  // delay slot nop
+                       : "=&r" (tmp), "=&r" (old), "=m" (*ptr)
+                       : "r" (new_value), "m" (*ptr)
+                       : "memory");
+
+  return old;
+}
+
+static INLINE Atomic32 AtomicIncrement(volatile Atomic32* ptr,
+                                       Atomic32 increment) {
+  Atomic32 tmp, res;
+
+  __asm__ __volatile__("1:\n"
+                       "ll %0, %2\n"  // tmp = *ptr
+                       "addu %0, %3\n"  // tmp = tmp + increment
+                       "move %1, %0\n"  // res = tmp
+                       "sc %0, %2\n"  // *ptr = tmp (with atomic check)
+                       "beqz %0, 1b\n"  // start again on atomic error
+                       "nop\n"  // delay slot nop
+                       : "=&r" (tmp), "=&r" (res), "=m" (*ptr)
+                       : "Ir" (increment), "m" (*ptr)
+                       : "memory");
+  // res now holds the final value.
+
+  return res;
+}
+
+#endif  /* NATIVE_CLIENT_SRC_INCLUDE_LINUX_MIPS_ATOMIC_OPS_LINUX_MIPS_H_ */