| OLD | NEW |
|---|
| (Empty) | |
| 1 diff -uNpr qemu-0.12.5/linux-user/main.c qemu-0.12.5_new/linux-user/main.c |
| 2 --- qemu-0.12.5/linux-user/main.c 2010-07-22 14:39:04.000000000 +0200 |
| 3 +++ qemu-0.12.5_new/linux-user/main.c 2011-08-01 16:05:35.651884528 +0200 |
| 4 @@ -33,6 +33,7 @@ |
| 5 |
| 6 |
| 7 #include "envlist.h" |
| 8 +#include <sys/resource.h> |
| 9 |
| 10 #define DEBUG_LOGFILE "/tmp/qemu.log" |
| 11 |
| 12 @@ -1916,7 +1917,21 @@ static const uint8_t mips_syscall_args[] |
| 13 MIPS_SYS(sys_getcpu, 3) |
| 14 MIPS_SYS(sys_epoll_pwait, 6) |
| 15 MIPS_SYS(sys_ioprio_set, 3) |
| 16 - MIPS_SYS(sys_ioprio_get, 2) |
| 17 + MIPS_SYS(sys_ioprio_get, 2) /* 4315 */ |
| 18 + MIPS_SYS(sys_utimensat, 4) |
| 19 + MIPS_SYS(sys_signalfd, 3) |
| 20 + MIPS_SYS(sys_timerfd, 0) |
| 21 + MIPS_SYS(sys_eventfd, 2) |
| 22 + MIPS_SYS(sys_fallocate, 4) /* 4320 */ |
| 23 + MIPS_SYS(sys_timerfd_create, 2) |
| 24 + MIPS_SYS(sys_timerfd_gettime, 2) |
| 25 + MIPS_SYS(sys_timerfd_settime, 4) |
| 26 + MIPS_SYS(sys_signalfd4, 4) |
| 27 + MIPS_SYS(sys_eventfd, 2) /* 4325 */ |
| 28 + MIPS_SYS(sys_epoll_create1, 1) |
| 29 + MIPS_SYS(sys_dup3, 3) |
| 30 + MIPS_SYS(do_pipe2, 2) |
| 31 + MIPS_SYS(sys_inotify_init1, 1) |
| 32 }; |
| 33 |
| 34 #undef MIPS_SYS |
| 35 @@ -2514,6 +2529,13 @@ void init_task_state(TaskState *ts) |
| 36 |
| 37 int main(int argc, char **argv, char **envp) |
| 38 { |
| 39 + #if defined(TARGET_MIPS) |
| 40 + { |
| 41 + //stack size 5MB |
| 42 + x86_stack_size = 5 * 1024 * 1024; |
| 43 + } |
| 44 + #endif //#if defined(TARGET_MIPS) |
| 45 + |
| 46 const char *filename; |
| 47 const char *cpu_model; |
| 48 struct target_pt_regs regs1, *regs = ®s1; |
| 49 @@ -2700,6 +2722,17 @@ int main(int argc, char **argv, char **e |
| 50 fprintf(stderr, "Unable to find CPU definition\n"); |
| 51 exit(1); |
| 52 } |
| 53 + |
| 54 +#if defined(TARGET_MIPS) |
| 55 + { |
| 56 + //Set OPEN_MAX on 1024 |
| 57 + struct rlimit rlim1; |
| 58 + rlim1.rlim_cur=1024; |
| 59 + rlim1.rlim_max=1024; |
| 60 + setrlimit(5, &rlim1); |
| 61 + } |
| 62 +#endif //#if defined(TARGET_MIPS) |
| 63 + |
| 64 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) |
| 65 cpu_reset(env); |
| 66 #endif |
| 67 diff -uNpr qemu-0.12.5/linux-user/strace.list qemu-0.12.5_new/linux-user/strace.
list |
| 68 --- qemu-0.12.5/linux-user/strace.list 2010-07-22 14:39:04.000000000 +0200 |
| 69 +++ qemu-0.12.5_new/linux-user/strace.list 2011-08-01 16:05:35.641884925 +0
200 |
| 70 @@ -1518,3 +1518,42 @@ |
| 71 #ifdef TARGET_NR_utimensat |
| 72 { TARGET_NR_utimensat, "utimensat", NULL, print_utimensat, NULL }, |
| 73 #endif |
| 74 +#ifdef TARGET_NR_signalfd |
| 75 +{ TARGET_NR_signalfd, "signalfd", NULL, NULL, NULL }, |
| 76 +#endif |
| 77 +#ifdef TARGET_NR_timerfd |
| 78 +{ TARGET_NR_timerfd, "timerfd", NULL, NULL, NULL }, |
| 79 +#endif |
| 80 +#ifdef TARGET_NR_eventfd |
| 81 +{ TARGET_NR_eventfd, "eventfd", NULL, NULL, NULL }, |
| 82 +#endif |
| 83 +#ifdef TARGET_NR_fallocate |
| 84 +{ TARGET_NR_fallocate, "fallocate", NULL, NULL, NULL }, |
| 85 +#endif |
| 86 +#ifdef TARGET_NR_timerfd_create |
| 87 +{ TARGET_NR_timerfd_create, "timerfd_create", NULL, NULL, NULL }, |
| 88 +#endif |
| 89 +#ifdef TARGET_NR_timerfd_gettime |
| 90 +{ TARGET_NR_timerfd_gettime, "timerfd_gettime", NULL, NULL, NULL }, |
| 91 +#endif |
| 92 +#ifdef TARGET_NR_timerfd_settime |
| 93 +{ TARGET_NR_timerfd_settime, "timerfd_settime", NULL, NULL, NULL }, |
| 94 +#endif |
| 95 +#ifdef TARGET_NR_signalfd4 |
| 96 +{ TARGET_NR_signalfd4, "signalfd4", NULL, NULL, NULL }, |
| 97 +#endif |
| 98 +#ifdef TARGET_NR_eventfd2 |
| 99 +{ TARGET_NR_eventfd2, "eventfd2", NULL, NULL, NULL }, |
| 100 +#endif |
| 101 +#ifdef TARGET_NR_epoll_create1 |
| 102 +{ TARGET_NR_epoll_create1, "epoll_create1", NULL, NULL, NULL }, |
| 103 +#endif |
| 104 +#ifdef TARGET_NR_dup3 |
| 105 +{ TARGET_NR_dup3, "dup3", NULL, NULL, NULL }, |
| 106 +#endif |
| 107 +#ifdef TARGET_NR_pipe2 |
| 108 +{ TARGET_NR_pipe2, "pipe2", NULL, NULL, NULL }, |
| 109 +#endif |
| 110 +#ifdef TARGET_NR_inotify_init1 |
| 111 +{ TARGET_NR_inotify_init1, "inotify_init1", NULL, NULL, NULL }, |
| 112 +#endif |
| 113 diff -uNpr qemu-0.12.5/linux-user/syscall.c qemu-0.12.5_new/linux-user/syscall.c |
| 114 --- qemu-0.12.5/linux-user/syscall.c 2010-07-22 14:39:04.000000000 +0200 |
| 115 +++ qemu-0.12.5_new/linux-user/syscall.c 2011-08-01 16:08:35.253009379 +0
200 |
| 116 @@ -62,6 +62,9 @@ |
| 117 #ifdef CONFIG_EVENTFD |
| 118 #include <sys/eventfd.h> |
| 119 #endif |
| 120 +#include <sys/epoll.h> |
| 121 +#include <sys/timerfd.h> |
| 122 +#include <sys/signalfd.h> |
| 123 |
| 124 #define termios host_termios |
| 125 #define winsize host_winsize |
| 126 @@ -967,7 +970,18 @@ static abi_long do_pipe(void *cpu_env, a |
| 127 return get_errno(ret); |
| 128 #if defined(TARGET_MIPS) |
| 129 ((CPUMIPSState*)cpu_env)->active_tc.gpr[3] = host_pipe[1]; |
| 130 - ret = host_pipe[0]; |
| 131 + if(!flags) |
| 132 + ret = host_pipe[0]; |
| 133 + |
| 134 + { |
| 135 + unsigned short val1=0; |
| 136 + val1 = (abi_long)(host_pipe[0] & 0xFFFFFFFF); |
| 137 + |
| 138 + abi_long *par; |
| 139 + *(&par) = (abi_long *)((CPUMIPSState*)cpu_env)->active_tc.gpr[4]; |
| 140 + par[0]= val1; |
| 141 + par[1]= host_pipe[1]; |
| 142 + } |
| 143 #elif defined(TARGET_SH4) |
| 144 ((CPUSH4State*)cpu_env)->gregs[1] = host_pipe[1]; |
| 145 ret = host_pipe[0]; |
| 146 @@ -2766,9 +2780,12 @@ static abi_long do_ipc(unsigned int call |
| 147 break; |
| 148 |
| 149 case IPCOP_semctl: |
| 150 - ret = do_semctl(first, second, third, (union target_semun)(abi_ulong) p
tr); |
| 151 - break; |
| 152 - |
| 153 + { |
| 154 + union target_semun *target_su; |
| 155 + target_su=(union target_semun *)(abi_ulong)ptr; |
| 156 + ret = do_semctl(first, second, third, *target_su); |
| 157 + break; |
| 158 + } |
| 159 case IPCOP_msgget: |
| 160 ret = get_errno(msgget(first, second)); |
| 161 break; |
| 162 @@ -3925,6 +3942,12 @@ static inline abi_long target_truncate64 |
| 163 arg3 = arg4; |
| 164 } |
| 165 #endif |
| 166 + |
| 167 +#ifdef TARGET_MIPS |
| 168 + arg2 = arg3; |
| 169 + arg3 = arg4; |
| 170 +#endif |
| 171 + |
| 172 return get_errno(truncate64(arg1, target_offset64(arg2, arg3))); |
| 173 } |
| 174 #endif |
| 175 @@ -3942,6 +3965,12 @@ static inline abi_long target_ftruncate6 |
| 176 arg3 = arg4; |
| 177 } |
| 178 #endif |
| 179 + |
| 180 +#ifdef TARGET_MIPS |
| 181 + arg2 = arg3; |
| 182 + arg3 = arg4; |
| 183 +#endif |
| 184 + |
| 185 return get_errno(ftruncate64(arg1, target_offset64(arg2, arg3))); |
| 186 } |
| 187 #endif |
| 188 @@ -5066,8 +5095,9 @@ abi_long do_syscall(void *cpu_env, int n |
| 189 struct rlimit rlim; |
| 190 if (!lock_user_struct(VERIFY_READ, target_rlim, arg2, 1)) |
| 191 goto efault; |
| 192 - rlim.rlim_cur = tswapl(target_rlim->rlim_cur); |
| 193 - rlim.rlim_max = tswapl(target_rlim->rlim_max); |
| 194 + rlim.rlim_cur = tswapl(target_rlim->rlim_cur) & 0xFFFFFFFF; |
| 195 + rlim.rlim_max = tswapl(target_rlim->rlim_max) & 0xFFFFFFFF; |
| 196 + |
| 197 unlock_user_struct(target_rlim, arg2, 0); |
| 198 ret = get_errno(setrlimit(resource, &rlim)); |
| 199 } |
| 200 @@ -5083,8 +5113,8 @@ abi_long do_syscall(void *cpu_env, int n |
| 201 if (!is_error(ret)) { |
| 202 if (!lock_user_struct(VERIFY_WRITE, target_rlim, arg2, 0)) |
| 203 goto efault; |
| 204 - target_rlim->rlim_cur = tswapl(rlim.rlim_cur); |
| 205 - target_rlim->rlim_max = tswapl(rlim.rlim_max); |
| 206 + target_rlim->rlim_cur = tswapl(rlim.rlim_cur) & 0x7FFFFFFF; |
| 207 + target_rlim->rlim_max = tswapl(rlim.rlim_max) & 0x7FFFFFFF; |
| 208 unlock_user_struct(target_rlim, arg2, 1); |
| 209 } |
| 210 } |
| 211 @@ -6115,13 +6145,21 @@ abi_long do_syscall(void *cpu_env, int n |
| 212 case TARGET_NR_pread64: |
| 213 if (!(p = lock_user(VERIFY_WRITE, arg2, arg3, 0))) |
| 214 goto efault; |
| 215 +#if defined(TARGET_MIPS) |
| 216 + ret = get_errno(pread64(arg1, p, arg3, target_offset64(arg5, arg4))); |
| 217 +#else |
| 218 ret = get_errno(pread64(arg1, p, arg3, target_offset64(arg4, arg5))); |
| 219 +#endif |
| 220 unlock_user(p, arg2, ret); |
| 221 break; |
| 222 case TARGET_NR_pwrite64: |
| 223 if (!(p = lock_user(VERIFY_READ, arg2, arg3, 1))) |
| 224 goto efault; |
| 225 +#if defined(TARGET_MIPS) |
| 226 + ret = get_errno(pwrite64(arg1, p, arg3, target_offset64(arg5, arg4))); |
| 227 +#else |
| 228 ret = get_errno(pwrite64(arg1, p, arg3, target_offset64(arg4, arg5))); |
| 229 +#endif |
| 230 unlock_user(p, arg2, 0); |
| 231 break; |
| 232 #endif |
| 233 @@ -6169,8 +6207,8 @@ abi_long do_syscall(void *cpu_env, int n |
| 234 struct target_rlimit *target_rlim; |
| 235 if (!lock_user_struct(VERIFY_WRITE, target_rlim, arg2, 0)) |
| 236 goto efault; |
| 237 - target_rlim->rlim_cur = tswapl(rlim.rlim_cur); |
| 238 - target_rlim->rlim_max = tswapl(rlim.rlim_max); |
| 239 + target_rlim->rlim_cur = tswapl(rlim.rlim_cur) & 0x7FFFFFFF; |
| 240 + target_rlim->rlim_max = tswapl(rlim.rlim_max) & 0x7FFFFFFF; |
| 241 unlock_user_struct(target_rlim, arg2, 1); |
| 242 } |
| 243 break; |
| 244 @@ -7032,6 +7070,108 @@ abi_long do_syscall(void *cpu_env, int n |
| 245 ret = get_errno(fallocate(arg1, arg2, arg3, arg4)); |
| 246 break; |
| 247 #endif |
| 248 +#if defined(TARGET_NR_signalfd) |
| 249 + case TARGET_NR_signalfd: |
| 250 + { |
| 251 + target_sigset_t *target_mask; |
| 252 + sigset_t mask; |
| 253 + if (!lock_user_struct(VERIFY_READ, target_mask, arg2, 1)) |
| 254 + goto efault; |
| 255 + |
| 256 + target_to_host_sigset(&mask, target_mask); |
| 257 + |
| 258 + unlock_user_struct(target_mask, arg2, 0); |
| 259 + ret = get_errno(signalfd(arg1, &mask, arg3)); |
| 260 + } |
| 261 + break; |
| 262 +#endif |
| 263 +#if defined(TARGET_NR_timerfd) |
| 264 + case TARGET_NR_timerfd: |
| 265 + goto unimplemented; |
| 266 + break; |
| 267 +#endif |
| 268 +#if defined(TARGET_NR_timerfd_create) |
| 269 + case TARGET_NR_timerfd_create: |
| 270 + ret = get_errno(timerfd_create(arg1, arg2)); |
| 271 + break; |
| 272 +#endif |
| 273 +#if defined(TARGET_NR_timerfd_gettime) |
| 274 + case TARGET_NR_timerfd_gettime: |
| 275 + { |
| 276 + struct itimerspec cur_timep_spec; |
| 277 + struct target_itimerspec *target_cur_timep_spec; |
| 278 + ret = get_errno(timerfd_gettime(arg1, &cur_timep_spec)); |
| 279 + if (!is_error(ret)) { |
| 280 + if (!lock_user_struct(VERIFY_WRITE, target_cur_timep_spec, arg2
, 0)) |
| 281 + goto efault; |
| 282 + |
| 283 + host_to_target_timespec((abi_long)&target_cur_timep_spec->it_in
terval, &cur_timep_spec.it_interval); |
| 284 + host_to_target_timespec((abi_long)&target_cur_timep_spec->it_va
lue, &cur_timep_spec.it_value); |
| 285 + |
| 286 + unlock_user_struct(target_cur_timep_spec, arg2, 1); |
| 287 + } |
| 288 + } |
| 289 + break; |
| 290 +#endif |
| 291 +#if defined(TARGET_NR_timerfd_settime) |
| 292 + case TARGET_NR_timerfd_settime: |
| 293 + { |
| 294 + int fd=arg1; |
| 295 + int flags=arg2; |
| 296 + |
| 297 + struct itimerspec new_timep_spec; |
| 298 + struct target_itimerspec *target_new_timep_spec; |
| 299 + if (!lock_user_struct(VERIFY_READ, target_new_timep_spec, arg3, 1)) |
| 300 + goto efault; |
| 301 + |
| 302 + target_to_host_timespec(&new_timep_spec.it_interval, (abi_long)&tar
get_new_timep_spec->it_interval); |
| 303 + target_to_host_timespec(&new_timep_spec.it_value, (abi_long)&target
_new_timep_spec->it_value); |
| 304 + |
| 305 + unlock_user_struct(target_new_timep_spec, arg3, 0); |
| 306 + |
| 307 + struct itimerspec old_timep_spec; |
| 308 + struct target_itimerspec *target_old_timep_spec; |
| 309 + |
| 310 + ret = get_errno(timerfd_settime(fd, flags, &new_timep_spec, &old_ti
mep_spec)); |
| 311 + |
| 312 + if (!is_error(ret) && arg4) { |
| 313 + if (!lock_user_struct(VERIFY_WRITE, target_old_timep_spec, arg4
+ sizeof(struct target_itimerspec), 0)) |
| 314 + goto efault; |
| 315 + host_to_target_timespec((abi_long)&target_old_timep_spec->it_in
terval, &old_timep_spec.it_interval); |
| 316 + host_to_target_timespec((abi_long)&target_old_timep_spec->it_va
lue, &old_timep_spec.it_value); |
| 317 + |
| 318 + unlock_user_struct(target_old_timep_spec, arg4, 1); |
| 319 + } |
| 320 + |
| 321 + } |
| 322 + break; |
| 323 +#endif |
| 324 +#if defined(TARGET_NR_signalfd4) |
| 325 + case TARGET_NR_signalfd4: |
| 326 + { |
| 327 + target_sigset_t *target_mask; |
| 328 + sigset_t mask; |
| 329 + if (!lock_user_struct(VERIFY_READ, target_mask, arg2, 1)) |
| 330 + goto efault; |
| 331 + |
| 332 + target_to_host_sigset(&mask, target_mask); |
| 333 + |
| 334 + unlock_user_struct(target_mask, arg2, 0); |
| 335 + ret = get_errno(signalfd(arg1, &mask, arg4)); |
| 336 + } |
| 337 + break; |
| 338 +#endif |
| 339 +#if defined(TARGET_NR_epoll_create1) |
| 340 + case TARGET_NR_epoll_create1: |
| 341 + ret = get_errno(epoll_create1(arg1)); |
| 342 + break; |
| 343 +#endif |
| 344 +#if defined(TARGET_NR_inotify_init1) |
| 345 + case TARGET_NR_inotify_init1: |
| 346 + ret = get_errno(inotify_init1(arg1)); |
| 347 + break; |
| 348 +#endif |
| 349 + |
| 350 default: |
| 351 unimplemented: |
| 352 gemu_log("qemu: Unsupported syscall: %d\n", num); |
| 353 diff -uNpr qemu-0.12.5/linux-user/syscall_defs.h qemu-0.12.5_new/linux-user/sysc
all_defs.h |
| 354 --- qemu-0.12.5/linux-user/syscall_defs.h 2010-07-22 14:39:04.000000000 +0
200 |
| 355 +++ qemu-0.12.5_new/linux-user/syscall_defs.h 2011-08-01 16:05:35.649884666 +0
200 |
| 356 @@ -2161,3 +2161,8 @@ struct target_mq_attr { |
| 357 #define FUTEX_CLOCK_REALTIME 256 |
| 358 #define FUTEX_CMD_MASK ~(FUTEX_PRIVATE_FLAG | FUTEX_CLOCK_REALTIME) |
| 359 |
| 360 + |
| 361 +struct target_itimerspec { |
| 362 + struct target_timespec it_interval; /* Interval for periodic timer */ |
| 363 + struct target_timespec it_value; /* Initial expiration */ |
| 364 +}; |
| 365 diff -ur qemu-0.12.5//target-mips/cpu.h qemu-mips.nacl/qemu-0.12.5//target-mips/
cpu.h |
| 366 --- qemu-0.12.5//target-mips/cpu.h 2010-07-22 14:39:04.000000000 +0200 |
| 367 +++ qemu-mips.nacl/qemu-0.12.5//target-mips/cpu.h 2012-06-15 12:18:16.9517
41355 +0200 |
| 368 @@ -613,4 +613,45 @@ |
| 369 env->tls_value = newtls; |
| 370 } |
| 371 |
| 372 +static inline void compute_hflags(CPUState *env) |
| 373 +{ |
| 374 + env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 375 + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
| 376 + MIPS_HFLAG_UX); |
| 377 + if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 378 + !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 379 + !(env->hflags & MIPS_HFLAG_DM)) { |
| 380 + env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
| 381 + } |
| 382 +#if defined(TARGET_MIPS64) |
| 383 + if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
| 384 + (env->CP0_Status & (1 << CP0St_PX)) || |
| 385 + (env->CP0_Status & (1 << CP0St_UX))) |
| 386 + env->hflags |= MIPS_HFLAG_64; |
| 387 + if (env->CP0_Status & (1 << CP0St_UX)) |
| 388 + env->hflags |= MIPS_HFLAG_UX; |
| 389 +#endif |
| 390 + if ((env->CP0_Status & (1 << CP0St_CU0)) || |
| 391 + !(env->hflags & MIPS_HFLAG_KSU)) |
| 392 + env->hflags |= MIPS_HFLAG_CP0; |
| 393 + if (env->CP0_Status & (1 << CP0St_CU1)) |
| 394 + env->hflags |= MIPS_HFLAG_FPU; |
| 395 + if (env->CP0_Status & (1 << CP0St_FR)) |
| 396 + env->hflags |= MIPS_HFLAG_F64; |
| 397 + if (env->insn_flags & ISA_MIPS32R2) { |
| 398 + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
| 399 + env->hflags |= MIPS_HFLAG_COP1X; |
| 400 + } else if (env->insn_flags & ISA_MIPS32) { |
| 401 + if (env->hflags & MIPS_HFLAG_64) |
| 402 + env->hflags |= MIPS_HFLAG_COP1X; |
| 403 + } else if (env->insn_flags & ISA_MIPS4) { |
| 404 + /* All supported MIPS IV CPUs use the XX (CU3) to enable |
| 405 + and disable the MIPS IV extensions to the MIPS III ISA. |
| 406 + Some other MIPS IV CPUs ignore the bit, so the check here |
| 407 + would be too restrictive for them. */ |
| 408 + if (env->CP0_Status & (1 << CP0St_CU3)) |
| 409 + env->hflags |= MIPS_HFLAG_COP1X; |
| 410 + } |
| 411 +} |
| 412 + |
| 413 #endif /* !defined (__MIPS_CPU_H__) */ |
| 414 diff -ur qemu-0.12.5//target-mips/exec.h qemu-mips.nacl/qemu-0.12.5//target-mips
/exec.h |
| 415 --- qemu-0.12.5//target-mips/exec.h 2010-07-22 14:39:04.000000000 +0200 |
| 416 +++ qemu-mips.nacl/qemu-0.12.5//target-mips/exec.h 2012-06-15 12:18:09.5597
41393 +0200 |
| 417 @@ -51,45 +51,4 @@ |
| 418 return EXCP_HALTED; |
| 419 } |
| 420 |
| 421 -static inline void compute_hflags(CPUState *env) |
| 422 -{ |
| 423 - env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 424 - MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
| 425 - MIPS_HFLAG_UX); |
| 426 - if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 427 - !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 428 - !(env->hflags & MIPS_HFLAG_DM)) { |
| 429 - env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
| 430 - } |
| 431 -#if defined(TARGET_MIPS64) |
| 432 - if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
| 433 - (env->CP0_Status & (1 << CP0St_PX)) || |
| 434 - (env->CP0_Status & (1 << CP0St_UX))) |
| 435 - env->hflags |= MIPS_HFLAG_64; |
| 436 - if (env->CP0_Status & (1 << CP0St_UX)) |
| 437 - env->hflags |= MIPS_HFLAG_UX; |
| 438 -#endif |
| 439 - if ((env->CP0_Status & (1 << CP0St_CU0)) || |
| 440 - !(env->hflags & MIPS_HFLAG_KSU)) |
| 441 - env->hflags |= MIPS_HFLAG_CP0; |
| 442 - if (env->CP0_Status & (1 << CP0St_CU1)) |
| 443 - env->hflags |= MIPS_HFLAG_FPU; |
| 444 - if (env->CP0_Status & (1 << CP0St_FR)) |
| 445 - env->hflags |= MIPS_HFLAG_F64; |
| 446 - if (env->insn_flags & ISA_MIPS32R2) { |
| 447 - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
| 448 - env->hflags |= MIPS_HFLAG_COP1X; |
| 449 - } else if (env->insn_flags & ISA_MIPS32) { |
| 450 - if (env->hflags & MIPS_HFLAG_64) |
| 451 - env->hflags |= MIPS_HFLAG_COP1X; |
| 452 - } else if (env->insn_flags & ISA_MIPS4) { |
| 453 - /* All supported MIPS IV CPUs use the XX (CU3) to enable |
| 454 - and disable the MIPS IV extensions to the MIPS III ISA. |
| 455 - Some other MIPS IV CPUs ignore the bit, so the check here |
| 456 - would be too restrictive for them. */ |
| 457 - if (env->CP0_Status & (1 << CP0St_CU3)) |
| 458 - env->hflags |= MIPS_HFLAG_COP1X; |
| 459 - } |
| 460 -} |
| 461 - |
| 462 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |
| 463 diff -ur qemu-0.12.5//target-mips/translate.c qemu-mips.nacl/qemu-0.12.5//target
-mips/translate.c |
| 464 --- qemu-0.12.5//target-mips/translate.c 2010-07-22 14:39:04.000000000 +0
200 |
| 465 +++ qemu-mips.nacl/qemu-0.12.5//target-mips/translate.c 2012-06-15 12:17:24.9277
43160 +0200 |
| 466 @@ -8614,6 +8614,7 @@ |
| 467 /* Reset registers to their default values */ |
| 468 env->CP0_PRid = env->cpu_model->CP0_PRid; |
| 469 env->CP0_Config0 = env->cpu_model->CP0_Config0; |
| 470 + env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; |
| 471 #ifdef TARGET_WORDS_BIGENDIAN |
| 472 env->CP0_Config0 |= (1 << CP0C0_BE); |
| 473 #endif |
| 474 @@ -8654,10 +8655,12 @@ |
| 475 |
| 476 #if defined(CONFIG_USER_ONLY) |
| 477 env->hflags = MIPS_HFLAG_UM; |
| 478 + env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); |
| 479 /* Enable access to the SYNCI_Step register. */ |
| 480 env->CP0_HWREna |= (1 << 1); |
| 481 if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
| 482 env->hflags |= MIPS_HFLAG_FPU; |
| 483 + env->CP0_Status |= (1 << CP0St_CU1); |
| 484 } |
| 485 #ifdef TARGET_MIPS64 |
| 486 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
| 487 @@ -8701,6 +8704,7 @@ |
| 488 env->hflags |= MIPS_HFLAG_64; |
| 489 } |
| 490 #endif |
| 491 + compute_hflags(env); |
| 492 env->exception_index = EXCP_NONE; |
| 493 } |
| 494 |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 10810038:
[MIPS] Patch for QEMU 0.12.5 for NaCl on MIPS. (Closed)
Base URL: http://src.chromium.org/native_client/trunk/src/third_party/