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Side by Side Diff: src/compiler/mips/instruction-codes-mips.h

Issue 998503002: MIPS: [turbofan] Unify Math.floor / Math.ceil optimization. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 22 matching lines...) Expand all
33 V(MipsMov) \ 33 V(MipsMov) \
34 V(MipsTst) \ 34 V(MipsTst) \
35 V(MipsCmp) \ 35 V(MipsCmp) \
36 V(MipsCmpD) \ 36 V(MipsCmpD) \
37 V(MipsAddD) \ 37 V(MipsAddD) \
38 V(MipsSubD) \ 38 V(MipsSubD) \
39 V(MipsMulD) \ 39 V(MipsMulD) \
40 V(MipsDivD) \ 40 V(MipsDivD) \
41 V(MipsModD) \ 41 V(MipsModD) \
42 V(MipsSqrtD) \ 42 V(MipsSqrtD) \
43 V(MipsFloat64Floor) \ 43 V(MipsFloat64RoundDown) \
44 V(MipsFloat64Ceil) \
45 V(MipsFloat64RoundTruncate) \ 44 V(MipsFloat64RoundTruncate) \
45 V(MipsFloat64RoundUp) \
46 V(MipsCvtSD) \ 46 V(MipsCvtSD) \
47 V(MipsCvtDS) \ 47 V(MipsCvtDS) \
48 V(MipsTruncWD) \ 48 V(MipsTruncWD) \
49 V(MipsTruncUwD) \ 49 V(MipsTruncUwD) \
50 V(MipsCvtDW) \ 50 V(MipsCvtDW) \
51 V(MipsCvtDUw) \ 51 V(MipsCvtDUw) \
52 V(MipsLb) \ 52 V(MipsLb) \
53 V(MipsLbu) \ 53 V(MipsLbu) \
54 V(MipsSb) \ 54 V(MipsSb) \
55 V(MipsLh) \ 55 V(MipsLh) \
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
88 #define TARGET_ADDRESSING_MODE_LIST(V) \ 88 #define TARGET_ADDRESSING_MODE_LIST(V) \
89 V(MRI) /* [%r0 + K] */ \ 89 V(MRI) /* [%r0 + K] */ \
90 V(MRR) /* [%r0 + %r1] */ 90 V(MRR) /* [%r0 + %r1] */
91 91
92 92
93 } // namespace compiler 93 } // namespace compiler
94 } // namespace internal 94 } // namespace internal
95 } // namespace v8 95 } // namespace v8
96 96
97 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 97 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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