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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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77 V(PPC_ExtendSignWord16) \ | 77 V(PPC_ExtendSignWord16) \ |
78 V(PPC_ExtendSignWord32) \ | 78 V(PPC_ExtendSignWord32) \ |
79 V(PPC_Uint32ToUint64) \ | 79 V(PPC_Uint32ToUint64) \ |
80 V(PPC_Int64ToInt32) \ | 80 V(PPC_Int64ToInt32) \ |
81 V(PPC_Int32ToFloat64) \ | 81 V(PPC_Int32ToFloat64) \ |
82 V(PPC_Uint32ToFloat64) \ | 82 V(PPC_Uint32ToFloat64) \ |
83 V(PPC_Float32ToFloat64) \ | 83 V(PPC_Float32ToFloat64) \ |
84 V(PPC_Float64ToInt32) \ | 84 V(PPC_Float64ToInt32) \ |
85 V(PPC_Float64ToUint32) \ | 85 V(PPC_Float64ToUint32) \ |
86 V(PPC_Float64ToFloat32) \ | 86 V(PPC_Float64ToFloat32) \ |
| 87 V(PPC_Float64ExtractLowWord32) \ |
| 88 V(PPC_Float64ExtractHighWord32) \ |
| 89 V(PPC_Float64InsertLowWord32) \ |
| 90 V(PPC_Float64InsertHighWord32) \ |
| 91 V(PPC_Float64Construct) \ |
87 V(PPC_LoadWordS8) \ | 92 V(PPC_LoadWordS8) \ |
88 V(PPC_LoadWordU8) \ | 93 V(PPC_LoadWordU8) \ |
89 V(PPC_LoadWordS16) \ | 94 V(PPC_LoadWordS16) \ |
90 V(PPC_LoadWordU16) \ | 95 V(PPC_LoadWordU16) \ |
91 V(PPC_LoadWordS32) \ | 96 V(PPC_LoadWordS32) \ |
92 V(PPC_LoadWord64) \ | 97 V(PPC_LoadWord64) \ |
93 V(PPC_LoadFloat32) \ | 98 V(PPC_LoadFloat32) \ |
94 V(PPC_LoadFloat64) \ | 99 V(PPC_LoadFloat64) \ |
95 V(PPC_StoreWord8) \ | 100 V(PPC_StoreWord8) \ |
96 V(PPC_StoreWord16) \ | 101 V(PPC_StoreWord16) \ |
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116 // MRR = [register + register] | 121 // MRR = [register + register] |
117 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 122 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
118 V(MRI) /* [%r0 + K] */ \ | 123 V(MRI) /* [%r0 + K] */ \ |
119 V(MRR) /* [%r0 + %r1] */ | 124 V(MRR) /* [%r0 + %r1] */ |
120 | 125 |
121 } // namespace compiler | 126 } // namespace compiler |
122 } // namespace internal | 127 } // namespace internal |
123 } // namespace v8 | 128 } // namespace v8 |
124 | 129 |
125 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ | 130 #endif // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_ |
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