Index: src/compiler/arm64/instruction-selector-arm64.cc |
diff --git a/src/compiler/arm64/instruction-selector-arm64.cc b/src/compiler/arm64/instruction-selector-arm64.cc |
index a27bd88733ee56e9ce8cdcfa40a7d4af3e63d114..b8805078138c45e02077f90228d62b90ef301eba 100644 |
--- a/src/compiler/arm64/instruction-selector-arm64.cc |
+++ b/src/compiler/arm64/instruction-selector-arm64.cc |
@@ -1033,6 +1033,20 @@ void InstructionSelector::VisitFloat64Add(Node* node) { |
void InstructionSelector::VisitFloat64Sub(Node* node) { |
+ Arm64OperandGenerator g(this); |
+ Float64BinopMatcher m(node); |
+ if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() && |
+ CanCover(m.node(), m.right().node())) { |
+ if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub && |
+ CanCover(m.right().node(), m.right().InputAt(0))) { |
+ Float64BinopMatcher mright0(m.right().InputAt(0)); |
+ if (mright0.left().IsMinusZero()) { |
+ Emit(kArm64Float64RoundUp, g.DefineAsRegister(node), |
+ g.UseRegister(mright0.right().node())); |
+ return; |
+ } |
+ } |
+ } |
VisitRRRFloat64(this, kArm64Float64Sub, node); |
} |
@@ -1060,13 +1074,8 @@ void InstructionSelector::VisitFloat64Sqrt(Node* node) { |
} |
-void InstructionSelector::VisitFloat64Floor(Node* node) { |
- VisitRRFloat64(this, kArm64Float64Floor, node); |
-} |
- |
- |
-void InstructionSelector::VisitFloat64Ceil(Node* node) { |
- VisitRRFloat64(this, kArm64Float64Ceil, node); |
+void InstructionSelector::VisitFloat64RoundDown(Node* node) { |
+ VisitRRFloat64(this, kArm64Float64RoundDown, node); |
} |
@@ -1613,8 +1622,7 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) { |
// static |
MachineOperatorBuilder::Flags |
InstructionSelector::SupportedMachineOperatorFlags() { |
- return MachineOperatorBuilder::kFloat64Floor | |
- MachineOperatorBuilder::kFloat64Ceil | |
+ return MachineOperatorBuilder::kFloat64RoundDown | |
MachineOperatorBuilder::kFloat64RoundTruncate | |
MachineOperatorBuilder::kFloat64RoundTiesAway | |
MachineOperatorBuilder::kWord32ShiftIsSafe | |