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Side by Side Diff: src/compiler/ia32/instruction-selector-ia32.cc

Issue 990963003: [turbofan] Unify Math.floor / Math.ceil optimization. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/instruction-selector-impl.h" 5 #include "src/compiler/instruction-selector-impl.h"
6 #include "src/compiler/node-matchers.h" 6 #include "src/compiler/node-matchers.h"
7 #include "src/compiler/node-properties.h" 7 #include "src/compiler/node-properties.h"
8 8
9 namespace v8 { 9 namespace v8 {
10 namespace internal { 10 namespace internal {
(...skipping 101 matching lines...) Expand 10 before | Expand all | Expand 10 after
112 return kMode_MR1; 112 return kMode_MR1;
113 } 113 }
114 } 114 }
115 115
116 bool CanBeBetterLeftOperand(Node* node) const { 116 bool CanBeBetterLeftOperand(Node* node) const {
117 return !selector()->IsLive(node); 117 return !selector()->IsLive(node);
118 } 118 }
119 }; 119 };
120 120
121 121
122 static void VisitRRFloat64(InstructionSelector* selector, ArchOpcode opcode, 122 static void VisitRRFloat64(InstructionSelector* selector,
123 Node* node) { 123 InstructionCode opcode, Node* node) {
124 IA32OperandGenerator g(selector); 124 IA32OperandGenerator g(selector);
125 selector->Emit(opcode, g.DefineAsRegister(node), 125 selector->Emit(opcode, g.DefineAsRegister(node),
126 g.UseRegister(node->InputAt(0))); 126 g.UseRegister(node->InputAt(0)));
127 } 127 }
128 128
129 129
130 void InstructionSelector::VisitLoad(Node* node) { 130 void InstructionSelector::VisitLoad(Node* node) {
131 MachineType rep = RepresentationOf(OpParameter<LoadRepresentation>(node)); 131 MachineType rep = RepresentationOf(OpParameter<LoadRepresentation>(node));
132 MachineType typ = TypeOf(OpParameter<LoadRepresentation>(node)); 132 MachineType typ = TypeOf(OpParameter<LoadRepresentation>(node));
133 133
(...skipping 505 matching lines...) Expand 10 before | Expand all | Expand 10 after
639 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); 639 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1)));
640 } else { 640 } else {
641 Emit(kSSEFloat64Add, g.DefineSameAsFirst(node), 641 Emit(kSSEFloat64Add, g.DefineSameAsFirst(node),
642 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); 642 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1)));
643 } 643 }
644 } 644 }
645 645
646 646
647 void InstructionSelector::VisitFloat64Sub(Node* node) { 647 void InstructionSelector::VisitFloat64Sub(Node* node) {
648 IA32OperandGenerator g(this); 648 IA32OperandGenerator g(this);
649 Float64BinopMatcher m(node);
650 if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() &&
651 CanCover(m.node(), m.right().node())) {
652 if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
653 CanCover(m.right().node(), m.right().InputAt(0))) {
654 Float64BinopMatcher mright0(m.right().InputAt(0));
655 if (mright0.left().IsMinusZero()) {
656 Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
657 g.DefineAsRegister(node), g.UseRegister(mright0.right().node()));
658 return;
659 }
660 }
661 }
649 if (IsSupported(AVX)) { 662 if (IsSupported(AVX)) {
650 Emit(kAVXFloat64Sub, g.DefineAsRegister(node), 663 Emit(kAVXFloat64Sub, g.DefineAsRegister(node),
651 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); 664 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1)));
652 } else { 665 } else {
653 Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node), 666 Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node),
654 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); 667 g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1)));
655 } 668 }
656 } 669 }
657 670
658 671
(...skipping 29 matching lines...) Expand all
688 temps); 701 temps);
689 } 702 }
690 703
691 704
692 void InstructionSelector::VisitFloat64Sqrt(Node* node) { 705 void InstructionSelector::VisitFloat64Sqrt(Node* node) {
693 IA32OperandGenerator g(this); 706 IA32OperandGenerator g(this);
694 Emit(kSSEFloat64Sqrt, g.DefineAsRegister(node), g.Use(node->InputAt(0))); 707 Emit(kSSEFloat64Sqrt, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
695 } 708 }
696 709
697 710
698 void InstructionSelector::VisitFloat64Floor(Node* node) { 711 void InstructionSelector::VisitFloat64RoundDown(Node* node) {
699 DCHECK(CpuFeatures::IsSupported(SSE4_1)); 712 VisitRRFloat64(this, kSSEFloat64Round | MiscField::encode(kRoundDown), node);
700 VisitRRFloat64(this, kSSEFloat64Floor, node);
701 }
702
703
704 void InstructionSelector::VisitFloat64Ceil(Node* node) {
705 DCHECK(CpuFeatures::IsSupported(SSE4_1));
706 VisitRRFloat64(this, kSSEFloat64Ceil, node);
707 } 713 }
708 714
709 715
710 void InstructionSelector::VisitFloat64RoundTruncate(Node* node) { 716 void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
711 DCHECK(CpuFeatures::IsSupported(SSE4_1)); 717 VisitRRFloat64(this, kSSEFloat64Round | MiscField::encode(kRoundToZero),
712 VisitRRFloat64(this, kSSEFloat64RoundTruncate, node); 718 node);
713 } 719 }
714 720
715 721
716 void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) { 722 void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
717 UNREACHABLE(); 723 UNREACHABLE();
718 } 724 }
719 725
720 726
721 void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) { 727 void InstructionSelector::VisitCall(Node* node, BasicBlock* handler) {
722 IA32OperandGenerator g(this); 728 IA32OperandGenerator g(this);
(...skipping 401 matching lines...) Expand 10 before | Expand all | Expand 10 after
1124 g.UseRegister(left), g.Use(right)); 1130 g.UseRegister(left), g.Use(right));
1125 } 1131 }
1126 1132
1127 1133
1128 // static 1134 // static
1129 MachineOperatorBuilder::Flags 1135 MachineOperatorBuilder::Flags
1130 InstructionSelector::SupportedMachineOperatorFlags() { 1136 InstructionSelector::SupportedMachineOperatorFlags() {
1131 MachineOperatorBuilder::Flags flags = 1137 MachineOperatorBuilder::Flags flags =
1132 MachineOperatorBuilder::kWord32ShiftIsSafe; 1138 MachineOperatorBuilder::kWord32ShiftIsSafe;
1133 if (CpuFeatures::IsSupported(SSE4_1)) { 1139 if (CpuFeatures::IsSupported(SSE4_1)) {
1134 flags |= MachineOperatorBuilder::kFloat64Floor | 1140 flags |= MachineOperatorBuilder::kFloat64RoundDown |
1135 MachineOperatorBuilder::kFloat64Ceil |
1136 MachineOperatorBuilder::kFloat64RoundTruncate; 1141 MachineOperatorBuilder::kFloat64RoundTruncate;
1137 } 1142 }
1138 return flags; 1143 return flags;
1139 } 1144 }
1140 1145
1141 } // namespace compiler 1146 } // namespace compiler
1142 } // namespace internal 1147 } // namespace internal
1143 } // namespace v8 1148 } // namespace v8
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