| Index: src/compiler/arm/instruction-selector-arm.cc
|
| diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
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| index e08226d5f3e44eed89f623d0882c4cf487ef24f6..5c8c7a1fd8643a5077d5e176525cff4cfd959bda 100644
|
| --- a/src/compiler/arm/instruction-selector-arm.cc
|
| +++ b/src/compiler/arm/instruction-selector-arm.cc
|
| @@ -1394,6 +1394,34 @@ void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
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| }
|
|
|
|
|
| +void InstructionSelector::VisitFloat64ExtractWord32(Node* node) {
|
| + ArmOperandGenerator g(this);
|
| + InstructionCode opcode =
|
| + (OpParameter<int>(node) == 0 ? kArmVmovLowU32F64 : kArmVmovHighU32F64);
|
| + Emit(opcode, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
|
| +}
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| +
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| +
|
| +void InstructionSelector::VisitFloat64InsertWord32(Node* node) {
|
| + ArmOperandGenerator g(this);
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| + Node* left = node->InputAt(0);
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| + Node* right = node->InputAt(1);
|
| + if (left->opcode() == IrOpcode::kFloat64InsertWord32 &&
|
| + OpParameter<int>(left) == 1 - OpParameter<int>(node) &&
|
| + CanCover(node, left)) {
|
| + left = left->InputAt(1);
|
| + if (OpParameter<int>(node) == 0) std::swap(left, right);
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| + Emit(kArmVmovF64U32U32, g.DefineAsRegister(node), g.UseRegister(left),
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| + g.UseRegister(right));
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| + return;
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| + }
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| + InstructionCode opcode =
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| + (OpParameter<int>(node) == 0) ? kArmVmovLowF64U32 : kArmVmovHighF64U32;
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| + Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left),
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| + g.UseRegister(right));
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| +}
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| +
|
| +
|
| // static
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| MachineOperatorBuilder::Flags
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| InstructionSelector::SupportedMachineOperatorFlags() {
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|
|