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Issue 974313002: [turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Addressed Svens comment. Created 5 years, 9 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after
56 V(ArmVfloorF64) \ 56 V(ArmVfloorF64) \
57 V(ArmVceilF64) \ 57 V(ArmVceilF64) \
58 V(ArmVroundTruncateF64) \ 58 V(ArmVroundTruncateF64) \
59 V(ArmVroundTiesAwayF64) \ 59 V(ArmVroundTiesAwayF64) \
60 V(ArmVcvtF32F64) \ 60 V(ArmVcvtF32F64) \
61 V(ArmVcvtF64F32) \ 61 V(ArmVcvtF64F32) \
62 V(ArmVcvtF64S32) \ 62 V(ArmVcvtF64S32) \
63 V(ArmVcvtF64U32) \ 63 V(ArmVcvtF64U32) \
64 V(ArmVcvtS32F64) \ 64 V(ArmVcvtS32F64) \
65 V(ArmVcvtU32F64) \ 65 V(ArmVcvtU32F64) \
66 V(ArmVmovLowU32F64) \
67 V(ArmVmovLowF64U32) \
68 V(ArmVmovHighU32F64) \
69 V(ArmVmovHighF64U32) \
70 V(ArmVmovF64U32U32) \
66 V(ArmVldrF32) \ 71 V(ArmVldrF32) \
67 V(ArmVstrF32) \ 72 V(ArmVstrF32) \
68 V(ArmVldrF64) \ 73 V(ArmVldrF64) \
69 V(ArmVstrF64) \ 74 V(ArmVstrF64) \
70 V(ArmLdrb) \ 75 V(ArmLdrb) \
71 V(ArmLdrsb) \ 76 V(ArmLdrsb) \
72 V(ArmStrb) \ 77 V(ArmStrb) \
73 V(ArmLdrh) \ 78 V(ArmLdrh) \
74 V(ArmLdrsh) \ 79 V(ArmLdrsh) \
75 V(ArmStrh) \ 80 V(ArmStrh) \
(...skipping 19 matching lines...) Expand all
95 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 100 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
96 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 101 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
97 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 102 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
98 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 103 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
99 104
100 } // namespace compiler 105 } // namespace compiler
101 } // namespace internal 106 } // namespace internal
102 } // namespace v8 107 } // namespace v8
103 108
104 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 109 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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