Subzero: Fix a register allocation issue for "advanced phi lowering".

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 861bc0e54ec75915fa3018320de4d452939dfae2..12c2f1c8f8e3f11e31f9cc570210de39cb00d6df 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -1691,10 +1691,19 @@ void TargetX8632::lowerAssign(const InstAssign *Inst) {
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
-    // If Dest is in memory, then RI is either a physical register or
-    // an immediate, otherwise RI can be anything.
-    Operand *RI =
-        legalize(Src0, Dest->hasReg() ? Legal_All : Legal_Reg | Legal_Imm);
+    Operand *RI;

[jvoung (off chromium), 2015/03/03 00:46:25]

Besides Phi, it does seem like this could affect load/store/bitcast also since
this is the generic lowerAssign(), so I wasn't too sure of the effect that this
would have. I guess worst case is, you get a dead assignment that's optimized
out.

[Jim Stichnoth, 2015/03/03 00:53:50]

For what it's worth, the asm code was the same before and after this change,
across Spec2k.  Yeah, the result is that the mov/movp below will be eliminated
as a redundant assignment.  However, assignments with precolored Dest operands
are rare: argument registers, return values, cl shift register, eax/edx
registers for mul/div, etc.

+    if (Dest->hasReg())
+      // If Dest already has a physical register, then legalize the
+      // Src operand into a Variable with the same register
+      // assignment.  This is mostly a workaround for advanced phi
+      // lowering's ad-hoc register allocation which assumes no
+      // register allocation is needed when at least one of the
+      // operands is non-memory.
+      RI = legalize(Src0, Legal_Reg, Dest->getRegNum());
+    else
+      // If Dest could be a stack operand, then RI must be a physical
+      // register or a scalar integer immediate.
+      RI = legalize(Src0, Legal_Reg | Legal_Imm);
     if (isVectorType(Dest->getType()))
       _movp(Dest, RI);
     else
@@ -4163,6 +4172,12 @@ namespace {
 bool isMemoryOperand(const Operand *Opnd) {
   if (const auto Var = llvm::dyn_cast<Variable>(Opnd))
     return !Var->hasReg();
+  // We treat vector undef values the same as a memory operand,
+  // because they do in fact need a register to materialize the vector
+  // of zeroes into.
+  if (llvm::isa<ConstantUndef>(Opnd))
+    return isScalarFloatingType(Opnd->getType()) ||
+           isVectorType(Opnd->getType());
   if (llvm::isa<Constant>(Opnd))
     return isScalarFloatingType(Opnd->getType());
   return true;