Subzero: Fix a register allocation issue for "advanced phi lowering".

src/IceTargetLoweringX8632.cpp

Index: src/IceTargetLoweringX8632.cpp
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 0576add554dd4fa18a98b822d0352596e5210586..c3189a0d2a9cbd4f5a3434c10c5519e1700cc5d8 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -1693,7 +1693,8 @@ void TargetX8632::lowerAssign(const InstAssign *Inst) {
     // If Dest is in memory, then RI is either a physical register or
     // an immediate, otherwise RI can be anything.

[jvoung (off chromium), 2015/03/02 19:27:56]

The "can be anything" comment seems to go with Legal_All, but it's no longer
Legal_All?

[Jim Stichnoth, 2015/03/02 23:33:53]

Done.

     Operand *RI =
-        legalize(Src0, Dest->hasReg() ? Legal_All : Legal_Reg | Legal_Imm);
+        legalize(Src0, Dest->hasReg() ? Legal_Reg : Legal_Reg | Legal_Imm,
+                 Dest->getRegNum());
     if (isVectorType(Dest->getType()))
       _movp(Dest, RI);
     else
@@ -4156,6 +4157,12 @@ namespace {
 bool isMemoryOperand(const Operand *Opnd) {
   if (const auto Var = llvm::dyn_cast<Variable>(Opnd))
     return !Var->hasReg();
+  // We treat vector undef values the same as a memory operand,
+  // because they do in fact need a register to materialize the vector
+  // of zeroes into.
+  if (llvm::isa<ConstantUndef>(Opnd))
+    return isScalarFloatingType(Opnd->getType()) ||
+           isVectorType(Opnd->getType());
   if (llvm::isa<Constant>(Opnd))
     return isScalarFloatingType(Opnd->getType());
   return true;