MIPS: Fix 'MIPS: [turbofan] Optimize certain chains of Branch into a Switch.'

src/compiler/mips64/code-generator-mips64.cc

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 7c1288d7549849cae10a892af9862fe0f528747d..60e016fa2281eed086be33ec69fbc65f9f2f1273 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -1044,9 +1044,10 @@ void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
   MipsOperandConverter i(this, instr);
   Register input = i.InputRegister(0);
   for (size_t index = 2; index < instr->InputCount(); index += 2) {
-    __ Branch(GetLabel(i.InputRpo(index + 1)), eq, input,
-              Operand(i.InputInt32(index + 0)));
+    __ li(at, Operand(i.InputInt32(index + 0)));
+    __ beq(input, at, GetLabel(i.InputRpo(index + 1)));
   }
+  __ nop();  // Branch delay slot of the last beq.
   AssembleArchJump(i.InputRpo(1));
 }
 
@@ -1058,16 +1059,16 @@ void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
   Label here;
 
   __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
-  // Ensure that dd-ed labels goes to 8 byte aligned addresses.
-  if ((masm()->pc_offset() & 7) == 0) {
+  __ BlockTrampolinePoolFor(case_count * 2 + 7);
+  // Ensure that dd-ed labels use 8 byte aligned addresses.
+  if ((masm()->pc_offset() & 7) != 0) {
     __ nop();
   }
   __ bal(&here);
-  __ nop();  // Branch delay slot nop.
+  __ dsll(at, input, 3);  // Branch delay slot.
   __ bind(&here);
-  __ dsll(at, input, 3);
   __ daddu(at, at, ra);
-  __ ld(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
+  __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
   __ jr(at);
   __ nop();  // Branch delay slot nop.
   for (size_t index = 0; index < case_count; ++index) {