| Index: lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp
|
| diff --git a/lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp b/lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp
|
| index 06e0a3e5121d2ef61b008198263ec68ba17df1a4..2e3e4e5449613b651b940d62e535109c8dd2402a 100644
|
| --- a/lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp
|
| +++ b/lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp
|
| @@ -490,7 +490,8 @@ bool CustomExpandInstNaClX86(const llvm::MCSubtargetInfo &STI,
|
| X86MCNaClSFIState &State) {
|
| // If we are emitting to .s, only sandbox pseudos not supported by gas.
|
| if (Out.hasRawTextSupport()) {
|
| - if (Inst.getOpcode() != X86::NACL_ANDSPi32)
|
| + if (!(Inst.getOpcode() == X86::NACL_ANDSPi8 ||
|
| + Inst.getOpcode() == X86::NACL_ANDSPi32))
|
| return false;
|
| }
|
| // If we make a call to EmitInstruction, we will be called recursively. In
|
| @@ -571,6 +572,10 @@ bool CustomExpandInstNaClX86(const llvm::MCSubtargetInfo &STI,
|
| assert(State.PrefixSaved == 0);
|
| EmitSPArith(STI, X86::SUB32ri, Inst.getOperand(0), Out);
|
| return true;
|
| + case X86::NACL_ANDSPi8:
|
| + assert(State.PrefixSaved == 0);
|
| + EmitSPArith(STI, X86::AND32ri8, Inst.getOperand(0), Out);
|
| + return true;
|
| case X86::NACL_ANDSPi32:
|
| assert(State.PrefixSaved == 0);
|
| EmitSPArith(STI, X86::AND32ri, Inst.getOperand(0), Out);
|
|
|