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1 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=// | 1 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=// |
2 // | 2 // |
3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file contains a pass that ensures stores and loads and stack/frame | 10 // This file contains a pass that ensures stores and loads and stack/frame |
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229 DebugLoc DL = MI.getDebugLoc(); | 229 DebugLoc DL = MI.getDebugLoc(); |
230 unsigned DestReg = MI.getOperand(0).getReg(); | 230 unsigned DestReg = MI.getOperand(0).getReg(); |
231 assert(DestReg == X86::ESP || DestReg == X86::RSP); | 231 assert(DestReg == X86::ESP || DestReg == X86::RSP); |
232 | 232 |
233 unsigned NewOpc = 0; | 233 unsigned NewOpc = 0; |
234 switch (Opc) { | 234 switch (Opc) { |
235 case X86::ADD64ri8 : NewOpc = X86::NACL_ASPi8; break; | 235 case X86::ADD64ri8 : NewOpc = X86::NACL_ASPi8; break; |
236 case X86::ADD64ri32: NewOpc = X86::NACL_ASPi32; break; | 236 case X86::ADD64ri32: NewOpc = X86::NACL_ASPi32; break; |
237 case X86::SUB64ri8 : NewOpc = X86::NACL_SSPi8; break; | 237 case X86::SUB64ri8 : NewOpc = X86::NACL_SSPi8; break; |
238 case X86::SUB64ri32: NewOpc = X86::NACL_SSPi32; break; | 238 case X86::SUB64ri32: NewOpc = X86::NACL_SSPi32; break; |
| 239 case X86::AND64ri8 : NewOpc = X86::NACL_ANDSPi8; break; |
239 case X86::AND64ri32: NewOpc = X86::NACL_ANDSPi32; break; | 240 case X86::AND64ri32: NewOpc = X86::NACL_ANDSPi32; break; |
240 } | 241 } |
241 if (NewOpc) { | 242 if (NewOpc) { |
242 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) | 243 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) |
243 .addImm(MI.getOperand(2).getImm()) | 244 .addImm(MI.getOperand(2).getImm()) |
244 .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15); | 245 .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15); |
245 MI.eraseFromParent(); | 246 MI.eraseFromParent(); |
246 return true; | 247 return true; |
247 } | 248 } |
248 | 249 |
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695 } | 696 } |
696 } | 697 } |
697 } | 698 } |
698 return Modified; | 699 return Modified; |
699 } | 700 } |
700 | 701 |
701 bool X86NaClRewritePass::runOnMachineFunction(MachineFunction &MF) { | 702 bool X86NaClRewritePass::runOnMachineFunction(MachineFunction &MF) { |
702 bool Modified = false; | 703 bool Modified = false; |
703 | 704 |
704 TM = &MF.getTarget(); | 705 TM = &MF.getTarget(); |
705 TII = TM->getInstrInfo(); | 706 TII = MF.getSubtarget().getInstrInfo(); |
706 TRI = TM->getRegisterInfo(); | 707 TRI = MF.getSubtarget().getRegisterInfo(); |
707 Subtarget = &TM->getSubtarget<X86Subtarget>(); | 708 Subtarget = &TM->getSubtarget<X86Subtarget>(); |
708 Is64Bit = Subtarget->is64Bit(); | 709 Is64Bit = Subtarget->is64Bit(); |
709 | 710 |
710 assert(Subtarget->isTargetNaCl() && "Unexpected target in NaClRewritePass!"); | 711 assert(Subtarget->isTargetNaCl() && "Unexpected target in NaClRewritePass!"); |
711 | 712 |
712 DEBUG(dbgs() << "*************** NaCl Rewrite Pass ***************\n"); | 713 DEBUG(dbgs() << "*************** NaCl Rewrite Pass ***************\n"); |
713 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); | 714 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); |
714 MFI != E; | 715 MFI != E; |
715 ++MFI) { | 716 ++MFI) { |
716 Modified |= runOnMachineBasicBlock(*MFI); | 717 Modified |= runOnMachineBasicBlock(*MFI); |
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742 } | 743 } |
743 return Modified; | 744 return Modified; |
744 } | 745 } |
745 | 746 |
746 /// createX86NaClRewritePassPass - returns an instance of the pass. | 747 /// createX86NaClRewritePassPass - returns an instance of the pass. |
747 namespace llvm { | 748 namespace llvm { |
748 FunctionPass* createX86NaClRewritePass() { | 749 FunctionPass* createX86NaClRewritePass() { |
749 return new X86NaClRewritePass(); | 750 return new X86NaClRewritePass(); |
750 } | 751 } |
751 } | 752 } |
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