PNaCl localmod mods in LLVM to 223109 (local files only)

lib/Target/X86/X86InstrNaCl.td

 //====- X86InstrNaCl.td - Describe NaCl Instructions ----*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the modifications to the X86 instruction set needed for
@@ skipping 88 matching lines @@
 
   def NACL_ASPi32: NaClPI64<(outs), (ins i64i32imm:$off, GR64:$rZP),
                    "naclasp{q}\t{$off, $rZP|$rZP, $off}">;
 
   def NACL_SSPi8 : NaClPI64<(outs), (ins i64i8imm:$off, GR64:$rZP),
                    "naclssp{q}\t{$off, $rZP|$rZP, $off}">;
 
   def NACL_SSPi32: NaClPI64<(outs), (ins i64i32imm:$off, GR64:$rZP),
                    "naclssp{q}\t{$off, $rZP|$rZP, $off}">;
 
+  def NACL_ANDSPi8: NaClPI64<(outs), (ins i64i8imm:$off, GR64:$rZP),
+                   "naclandsp{q}\t{$off, $rZP|$rZP, $off}">;
+
   def NACL_ANDSPi32: NaClPI64<(outs), (ins i64i32imm:$off, GR64:$rZP),
                    "naclandsp{q}\t{$off, $rZP|$rZP, $off}">;
 }
 
 let Defs = [RSP], Uses = [RBP], isAsmParserOnly = 1 in {
   def NACL_SPADJi32  : NaClPI64<(outs), (ins i64i32imm:$off, GR64:$rZP),
                        "naclspadj\t{$off, $rZP|$rZP, $off}">;
 }
 
 let Defs = [RSP], isAsmParserOnly = 1 in {
@@ skipping 120 matching lines @@
 
 let usesCustomInserter = 1, Defs = [EFLAGS] in
 def NACL_CG_VAARG_64 : I<0, Pseudo,
                      (outs GR32:$dst),
                      (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
                      "#NACL_VAARG_64 $dst, $ap, $size, $mode, $align",
                      [(set GR32:$dst,
                      (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
                      (implicit EFLAGS)]>,
                      Requires<[IsNaCl, In64BitMode]>;