Index: lib/Target/ARM/ARMBaseInstrInfo.cpp |
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp |
index 7a315c4b2ef5c27152ad3c86c30806dc6a97bfcf..8bbd209d46306d3d55661e06e8db6dd2415fe9dc 100644 |
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp |
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp |
@@ -2394,7 +2394,8 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, |
else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) { |
// Conservatively refuse to convert an instruction which isn't in the same |
// BB as the comparison. |
- // For CMPri, we need to check Sub, thus we can't return here. |
+ // For CMPri w/ CmpValue != 0, a Sub may still be a candidate. |
+ // Thus we cannot return here. |
if (CmpInstr->getOpcode() == ARM::CMPri || |
CmpInstr->getOpcode() == ARM::t2CMPri) |
MI = nullptr; |
@@ -2473,8 +2474,8 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, |
case ARM::t2EORrr: |
case ARM::t2EORri: { |
// Scan forward for the use of CPSR |
- // When checking against MI: if it's a conditional code requires |
- // checking of V bit, then this is not safe to do. |
+ // When checking against MI: if it's a conditional code that requires |
+ // checking of the V bit or C bit, then this is not safe to do. |
// It is safe to remove CmpInstr if CPSR is redefined or killed. |
// If we are done with the basic block, we need to check whether CPSR is |
// live-out. |
@@ -2541,19 +2542,30 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, |
OperandsToUpdate.push_back( |
std::make_pair(&((*I).getOperand(IO - 1)), NewCC)); |
} |
- } else |
+ } else { |
+ // No Sub, so this is x = <op> y, z; cmp x, 0. |
switch (CC) { |
- default: |
+ case ARMCC::EQ: // Z |
+ case ARMCC::NE: // Z |
+ case ARMCC::MI: // N |
+ case ARMCC::PL: // N |
+ case ARMCC::AL: // none |
// CPSR can be used multiple times, we should continue. |
break; |
- case ARMCC::VS: |
- case ARMCC::VC: |
- case ARMCC::GE: |
- case ARMCC::LT: |
- case ARMCC::GT: |
- case ARMCC::LE: |
+ case ARMCC::HS: // C |
+ case ARMCC::LO: // C |
+ case ARMCC::VS: // V |
+ case ARMCC::VC: // V |
+ case ARMCC::HI: // C Z |
+ case ARMCC::LS: // C Z |
+ case ARMCC::GE: // N V |
+ case ARMCC::LT: // N V |
+ case ARMCC::GT: // Z N V |
+ case ARMCC::LE: // Z N V |
+ // The instruction uses the V bit or C bit which is not safe. |
return false; |
} |
+ } |
} |
} |