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| 1 ; Tests that vector operations survive through PNaCl bitcode files. |
| 2 |
| 3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \ |
| 4 ; RUN: | FileCheck %s |
| 5 |
| 6 define internal void @loadstore(i32 %addr) { ; CHECK-LABEL: loadstore |
| 7 %ptr16xi8 = inttoptr i32 %addr to <16 x i8>* ; CHECK-NEXT: %[[ptr16xi8:
[0-9]+]] = inttoptr i32 %[[addr:[0-9]+]] to <16 x i8>* |
| 8 %l16xi8 = load <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: %[[l16xi8:[0
-9]+]] = load <16 x i8>* %[[ptr16xi8]], align 1 |
| 9 %ptr8xi16 = inttoptr i32 %addr to <8 x i16>* ; CHECK-NEXT: %[[ptr8xi16:
[0-9]+]] = inttoptr i32 %[[addr]] to <8 x i16>* |
| 10 %l8xi16 = load <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: %[[l8xi16:[0
-9]+]] = load <8 x i16>* %[[ptr8xi16]], align 2 |
| 11 %ptr4xi32 = inttoptr i32 %addr to <4 x i32>* ; CHECK-NEXT: %[[ptr4xi32:
[0-9]+]] = inttoptr i32 %[[addr]] to <4 x i32>* |
| 12 %l4xi32 = load <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: %[[l4xi32:[0
-9]+]] = load <4 x i32>* %[[ptr4xi32]], align 4 |
| 13 %ptr4xfloat = inttoptr i32 %addr to <4 x float>* ; CHECK-NEXT: %[[ptr4xfloa
t:[0-9]+]] = inttoptr i32 %[[addr]] to <4 x float>* |
| 14 %l4xfloat = load <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: %[[l4xfloat:
[0-9]+]] = load <4 x float>* %[[ptr4xfloat]], align 4 |
| 15 |
| 16 store <16 x i8> undef, <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: store
<16 x i8> undef, <16 x i8>* %[[ptr16xi8]], align 1 |
| 17 store <8 x i16> undef, <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: store
<8 x i16> undef, <8 x i16>* %[[ptr8xi16]], align 2 |
| 18 store <4 x i32> undef, <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: store
<4 x i32> undef, <4 x i32>* %[[ptr4xi32]], align 4 |
| 19 store <4 x float> undef, <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: store
<4 x float> undef, <4 x float>* %[[ptr4xfloat]], align 4 |
| 20 |
| 21 ret void ; CHECK-NEXT: ret void |
| 22 } |
| 23 |
| 24 define internal void @binops() { ; CHECK-LABEL: binops |
| 25 %1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, un
def |
| 26 %2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef,
undef |
| 27 %3 = sub <4 x i32> undef, undef ; CHECK-NEXT: %3 = sub <4 x i32> undef, un
def |
| 28 %4 = fsub <4 x float> undef, undef ; CHECK-NEXT: %4 = fsub <4 x float> undef,
undef |
| 29 %5 = mul <4 x i32> undef, undef ; CHECK-NEXT: %5 = mul <4 x i32> undef, un
def |
| 30 %6 = fmul <4 x float> undef, undef ; CHECK-NEXT: %6 = fmul <4 x float> undef,
undef |
| 31 %7 = udiv <4 x i32> undef, undef ; CHECK-NEXT: %7 = udiv <4 x i32> undef, u
ndef |
| 32 %8 = sdiv <4 x i32> undef, undef ; CHECK-NEXT: %8 = sdiv <4 x i32> undef, u
ndef |
| 33 %9 = fdiv <4 x float> undef, undef ; CHECK-NEXT: %9 = fdiv <4 x float> undef,
undef |
| 34 %10 = urem <4 x i32> undef, undef ; CHECK-NEXT: %10 = urem <4 x i32> undef,
undef |
| 35 %11 = srem <4 x i32> undef, undef ; CHECK-NEXT: %11 = srem <4 x i32> undef,
undef |
| 36 %12 = frem <4 x float> undef, undef ; CHECK-NEXT: %12 = frem <4 x float> undef
, undef |
| 37 %13 = shl <4 x i32> undef, undef ; CHECK-NEXT: %13 = shl <4 x i32> undef, u
ndef |
| 38 %14 = lshr <4 x i32> undef, undef ; CHECK-NEXT: %14 = lshr <4 x i32> undef,
undef |
| 39 %15 = ashr <4 x i32> undef, undef ; CHECK-NEXT: %15 = ashr <4 x i32> undef,
undef |
| 40 %16 = and <4 x i32> undef, undef ; CHECK-NEXT: %16 = and <4 x i32> undef, u
ndef |
| 41 %17 = or <4 x i32> undef, undef ; CHECK-NEXT: %17 = or <4 x i32> undef, un
def |
| 42 %18 = xor <4 x i32> undef, undef ; CHECK-NEXT: %18 = xor <4 x i32> undef, u
ndef |
| 43 %19 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef ; CHECK-NEXT: %1
9 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef |
| 44 ret void ; CHECK-NEXT: ret void |
| 45 } |
| 46 |
| 47 define internal void @insert_extract() { ; CHECK-LABEL: insert_extract |
| 48 %1 = extractelement <4 x i32> undef, i32 0 ; CHECK-NEXT: %1 = extractele
ment <4 x i32> undef, i32 0 |
| 49 %2 = extractelement <4 x i32> undef, i32 1 ; CHECK-NEXT: %2 = extractele
ment <4 x i32> undef, i32 1 |
| 50 %3 = extractelement <4 x i32> undef, i32 2 ; CHECK-NEXT: %3 = extractele
ment <4 x i32> undef, i32 2 |
| 51 %4 = extractelement <4 x i32> undef, i32 3 ; CHECK-NEXT: %4 = extractele
ment <4 x i32> undef, i32 3 |
| 52 %5 = insertelement <4 x i32> undef, i32 1, i32 0 ; CHECK-NEXT: %5 = insertelem
ent <4 x i32> undef, i32 1, i32 0 |
| 53 %6 = insertelement <4 x i32> undef, i32 1, i32 1 ; CHECK-NEXT: %6 = insertelem
ent <4 x i32> undef, i32 1, i32 1 |
| 54 %7 = insertelement <4 x i32> undef, i32 1, i32 2 ; CHECK-NEXT: %7 = insertelem
ent <4 x i32> undef, i32 1, i32 2 |
| 55 %8 = insertelement <4 x i32> undef, i32 1, i32 3 ; CHECK-NEXT: %8 = insertelem
ent <4 x i32> undef, i32 1, i32 3 |
| 56 ret void ; CHECK-NEXT: ret void |
| 57 } |
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