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| 1 ; Test that intrinsic declarations are read back correctly. |
| 2 |
| 3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw \ |
| 4 ; RUN: | llvm-dis - | FileCheck %s -check-prefix=TD |
| 5 |
| 6 declare i8* @llvm.stacksave() |
| 7 declare void @llvm.stackrestore(i8*) |
| 8 |
| 9 declare i8* @llvm.nacl.read.tp() |
| 10 declare void @llvm.nacl.longjmp(i8*, i32) |
| 11 declare i32 @llvm.nacl.setjmp(i8*) |
| 12 |
| 13 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
i1) |
| 14 declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
i1) |
| 15 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) |
| 16 |
| 17 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) |
| 18 declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) |
| 19 |
| 20 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) |
| 21 declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32) |
| 22 |
| 23 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) |
| 24 declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32) |
| 25 |
| 26 declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) |
| 27 declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) |
| 28 |
| 29 declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*) |
| 30 |
| 31 |
| 32 ; TD: declare i8* @llvm.stacksave() |
| 33 ; TD: declare void @llvm.stackrestore(i8*) |
| 34 |
| 35 ; TD: declare i8* @llvm.nacl.read.tp() |
| 36 ; TD: declare void @llvm.nacl.longjmp(i8*, i32) |
| 37 ; TD: declare i32 @llvm.nacl.setjmp(i8*) |
| 38 |
| 39 ; TD: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* {{.*}}, i8* {{.*}}, i32, i32,
i1) |
| 40 ; TD: declare void @llvm.memmove.p0i8.p0i8.i32(i8* {{.*}}, i8* {{.*}}, i32, i32,
i1) |
| 41 ; TD: declare void @llvm.memset.p0i8.i32(i8* {{.*}}, i8, i32, i32, i1) |
| 42 |
| 43 ; TD: declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) |
| 44 ; TD: declare i64 @llvm.nacl.atomic.load.i64(i64*, i32) |
| 45 |
| 46 ; TD: declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) |
| 47 ; TD: declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32) |
| 48 |
| 49 ; TD: declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) |
| 50 ; TD: declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32) |
| 51 |
| 52 ; TD: declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) |
| 53 ; TD: declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) |
| 54 |
| 55 ; TD: declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*) |
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