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Issue 939073008: Rebased PNaCl localmods in LLVM to 223109 (Closed)
Patch Set: undo localmod Created 5 years, 10 months ago
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1 ; RUN: pnacl-llc -mtriple=armv7-unknown-nacl -mattr=+neon -filetype=obj %s -o - \
2 ; RUN: | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
3
4 define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
5 %tmp1 = load <8 x i8>* %B
6 %tmp2 = extractelement <8 x i8> %tmp1, i32 3
7 store i8 %tmp2, i8* %A, align 8
8 ; CHECK: bic r0, r0, #3221225472
9 ; CHECK-NEXT: vst1.8 {d{{[0-9]+}}[3]}, [r0]
10 ret void
11 }
12
13 define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
14 %tmp1 = load <4 x i16>* %B
15 %tmp2 = extractelement <4 x i16> %tmp1, i32 2
16 store i16 %tmp2, i16* %A, align 8
17 ; CHECK: bic r0, r0, #3221225472
18 ; CHECK-NEXT: vst1.16 {d{{[0-9]+}}[2]}, [r0:16]
19 ret void
20 }
21
22 define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
23 %tmp1 = load <2 x i32>* %B
24 %tmp2 = extractelement <2 x i32> %tmp1, i32 1
25 store i32 %tmp2, i32* %A, align 8
26 ; CHECK: bic r0, r0, #3221225472
27 ; CHECK-NEXT: vst1.32 {d{{[0-9]+}}[1]}, [r0:32]
28 ret void
29 }
30
31 define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
32 %tmp1 = load <16 x i8>* %B
33 ; CHECK: bic r1, r1, #3221225472
34 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
35 %tmp2 = extractelement <16 x i8> %tmp1, i32 9
36 store i8 %tmp2, i8* %A, align 8
37 ; CHECK: bic r0, r0, #3221225472
38 ; CHECK-NEXT: vst1.8 {d{{[0-9]+}}[1]}, [r0]
39 ret void
40 }
41
42 define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
43 %tmp1 = load <8 x i16>* %B
44 ; CHECK: bic r1, r1, #3221225472
45 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
46 %tmp2 = extractelement <8 x i16> %tmp1, i32 5
47 store i16 %tmp2, i16* %A, align 8
48 ; CHECK: bic r0, r0, #3221225472
49 ; CHECK-NEXT: vst1.16 {d{{[0-9]+}}[1]}, [r0:16]
50 ret void
51 }
52
53 define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
54 %tmp1 = load <8 x i8>* %B
55 call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
56 ; CHECK: bic r0, r0, #3221225472
57 ; CHECK-NEXT: vst2.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:16]
58 ret void
59 }
60
61 define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
62 %tmp0 = bitcast i16* %A to i8*
63 %tmp1 = load <4 x i16>* %B
64 call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
65 ; CHECK: bic r0, r0, #3221225472
66 ; CHECK-NEXT: vst2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0:32]
67 ret void
68 }
69
70 define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
71 %tmp0 = bitcast i32* %A to i8*
72 %tmp1 = load <2 x i32>* %B
73 call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
74 ; CHECK: bic r0, r0, #3221225472
75 ; CHECK-NEXT: vst2.32 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
76 ret void
77 }
78
79 define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
80 %tmp0 = bitcast i16* %A to i8*
81 %tmp1 = load <8 x i16>* %B
82 ; CHECK: bic r1, r1, #3221225472
83 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
84 call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
85 ; CHECK: bic r0, r0, #3221225472
86 ; CHECK-NEXT: vst2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
87 ret void
88 }
89
90 define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
91 %tmp0 = bitcast i32* %A to i8*
92 %tmp1 = load <4 x i32>* %B
93 ; CHECK: bic r1, r1, #3221225472
94 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
95 call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
96 ; CHECK: bic r0, r0, #3221225472
97 ; CHECK-NEXT: vst2.32 {d{{[0-9]+}}[0], d{{[0-9]+}}[0]}, [r0:64]
98 ret void
99 }
100
101 define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
102 %tmp1 = load <8 x i8>* %B
103 call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
104 ; CHECK: bic r0, r0, #3221225472
105 ; CHECK-NEXT: vst3.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
106 ret void
107 }
108
109 define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
110 %tmp0 = bitcast i16* %A to i8*
111 %tmp1 = load <4 x i16>* %B
112 call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
113 ; CHECK: bic r0, r0, #3221225472
114 ; CHECK-NEXT: vst3.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
115 ret void
116 }
117
118 define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
119 %tmp0 = bitcast i32* %A to i8*
120 %tmp1 = load <2 x i32>* %B
121 call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
122 ; CHECK: bic r0, r0, #3221225472
123 ; CHECK-NEXT: vst3.32 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0]
124 ret void
125 }
126
127 define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
128 %tmp1 = load <8 x i8>* %B
129 call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
130 ; CHECK: bic r0, r0, #3221225472
131 ; CHECK-NEXT: vst4.8 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9 ]+}}[1]}, [r0:32]
132 ret void
133 }
134
135 define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
136 %tmp0 = bitcast i16* %A to i8*
137 %tmp1 = load <4 x i16>* %B
138 call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
139 ; CHECK: bic r0, r0, #3221225472
140 ; CHECK-NEXT: vst4.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0- 9]+}}[1]}, [r0]
141 ret void
142 }
143
144 define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
145 %tmp0 = bitcast i32* %A to i8*
146 %tmp1 = load <2 x i32>* %B
147 call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
148 ; CHECK: bic r0, r0, #3221225472
149 ; CHECK-NEXT: vst4.32 {d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0-9]+}}[1], d{{[0- 9]+}}[1]}, [r0:128]
150 ret void
151 }
152
153 define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
154 %tmp0 = bitcast i16* %A to i8*
155 %tmp1 = load <8 x i16>* %B
156 ; CHECK: bic r1, r1, #3221225472
157 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
158 call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
159 ; CHECK: bic r0, r0, #3221225472
160 ; CHECK-NEXT: vst4.16 {d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0-9]+}}[3], d{{[0- 9]+}}[3]}, [r0:64]
161 ret void
162 }
163
164 define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
165 %tmp0 = bitcast i32* %A to i8*
166 %tmp1 = load <4 x i32>* %B
167 ; CHECK: bic r1, r1, #3221225472
168 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
169 call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
170 ; CHECK: bic r0, r0, #3221225472
171 ; CHECK-NEXT: vst4.32 {d{{[0-9]+}}[0], d{{[0-9]+}}[0], d{{[0-9]+}}[0], d{{[0- 9]+}}[0]}, [r0]
172 ret void
173 }
174
175 declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nou nwind
176 declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind
177 declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind
178 declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i 32) nounwind
179 declare void @llvm.arm.neon.vst2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind
180 declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind
181 declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i 32) nounwind
182 declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32 , i32) nounwind
183 declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
184 declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
185 declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x f loat>, i32, i32) nounwind
186 declare void @llvm.arm.neon.vst3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
187 declare void @llvm.arm.neon.vst3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
188 declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f loat>, i32, i32) nounwind
189 declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
190 declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
191 declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
192 declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x f loat>, <2 x float>, i32, i32) nounwind
193 declare void @llvm.arm.neon.vst4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
194 declare void @llvm.arm.neon.vst4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
195 declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f loat>, <4 x float>, i32, i32) nounwind
196
197 ;Check for a post-increment updating store with register increment.
198 define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
199 ; CHECK: bic r1, r1, #3221225472
200 %A = load i16** %ptr
201 %tmp0 = bitcast i16* %A to i8*
202 %tmp1 = load <4 x i16>* %B
203 call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
204 ; CHECK: bic r1, r1, #3221225472
205 ; CHECK-NEXT: vst2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r1], r2
206 %tmp2 = getelementptr i16* %A, i32 %inc
207 store i16* %tmp2, i16** %ptr
208 ret void
209 }
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