Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(39)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: test/NaCl/ARM/neon-vst1-sandboxing.ll

Issue 939073008: Rebased PNaCl localmods in LLVM to 223109 (Closed)
Patch Set: undo localmod Created 5 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « test/NaCl/ARM/neon-vldlane-sandboxing.ll ('k') | test/NaCl/ARM/neon-vst2-sandboxing.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
(Empty)
1 ; RUN: pnacl-llc -mtriple=armv7-unknown-nacl -mattr=+neon -filetype=obj %s -o - \
2 ; RUN: | llvm-objdump -disassemble -triple armv7 - | FileCheck %s
3
4 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
5 %tmp1 = load <8 x i8>* %B
6 call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
7 ; CHECK: bic r0, r0, #3221225472
8 ; CHECK-NEXT: vst1.8 {{{d[0-9]+}}}, [r0:64]
9 ret void
10 }
11
12 define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
13 %tmp0 = bitcast i16* %A to i8*
14 %tmp1 = load <4 x i16>* %B
15 call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1)
16 ; CHECK: bic r0, r0, #3221225472
17 ; CHECK-NEXT: vst1.16 {{{d[0-9]+}}}, [r0]
18 ret void
19 }
20
21 define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
22 %tmp0 = bitcast i32* %A to i8*
23 %tmp1 = load <2 x i32>* %B
24 call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1)
25 ; CHECK: bic r0, r0, #3221225472
26 ; CHECK-NEXT: vst1.32 {{{d[0-9]+}}}, [r0]
27 ret void
28 }
29
30 define void @vst1f(float* %A, <2 x float>* %B) nounwind {
31 %tmp0 = bitcast float* %A to i8*
32 %tmp1 = load <2 x float>* %B
33 call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
34 ; CHECK: bic r0, r0, #3221225472
35 ; CHECK-NEXT: vst1.32 {{{d[0-9]+}}}, [r0]
36 ret void
37 }
38
39 define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
40 %tmp0 = bitcast i64* %A to i8*
41 %tmp1 = load <1 x i64>* %B
42 call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1)
43 ; CHECK: bic r0, r0, #3221225472
44 ; CHECK-NEXT: vst1.64 {{{d[0-9]+}}}, [r0]
45 ret void
46 }
47
48 define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
49 %tmp1 = load <16 x i8>* %B
50 ; CHECK: bic r1, r1, #3221225472
51 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
52 call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
53 ; CHECK: bic r0, r0, #3221225472
54 ; CHECK-NEXT: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:64]
55 ret void
56 }
57
58 define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
59 %tmp0 = bitcast i16* %A to i8*
60 %tmp1 = load <8 x i16>* %B
61 ; CHECK: bic r1, r1, #3221225472
62 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
63 call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
64 ; CHECK: bic r0, r0, #3221225472
65 ; CHECK-NEXT: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [r0:128]
66 ret void
67 }
68
69 define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
70 %tmp0 = bitcast i32* %A to i8*
71 %tmp1 = load <4 x i32>* %B
72 ; CHECK: bic r1, r1, #3221225472
73 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
74 call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1)
75 ; CHECK: bic r0, r0, #3221225472
76 ; CHECK-NEXT: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0]
77 ret void
78 }
79
80 define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
81 %tmp0 = bitcast float* %A to i8*
82 %tmp1 = load <4 x float>* %B
83 ; CHECK: bic r1, r1, #3221225472
84 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
85 call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1)
86 ; CHECK: bic r0, r0, #3221225472
87 ; CHECK-NEXT: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0]
88 ret void
89 }
90
91 define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
92 %tmp0 = bitcast i64* %A to i8*
93 %tmp1 = load <2 x i64>* %B
94 ; CHECK: bic r1, r1, #3221225472
95 ; CHECK-NEXT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
96 call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
97 ; CHECK: bic r0, r0, #3221225472
98 ; CHECK-NEXT: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r0]
99 ret void
100 }
101
102 ;Check for a post-increment updating store.
103 define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
104 ; CHECK: bic r1, r1, #3221225472
105 %A = load float** %ptr
106 %tmp0 = bitcast float* %A to i8*
107 %tmp1 = load <2 x float>* %B
108 call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
109 ; CHECK: bic r1, r1, #3221225472
110 ; CHECK-NEXT: vst1.32 {{{d[0-9]+}}}, [r1]!
111 %tmp2 = getelementptr float* %A, i32 2
112 store float* %tmp2, float** %ptr
113 ret void
114 }
115
116 declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
117 declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind
118 declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind
119 declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind
120 declare void @llvm.arm.neon.vst1.v1i64(i8*, <1 x i64>, i32) nounwind
121
122 declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind
123 declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind
124 declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind
125 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
126 declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind
127
OLDNEW
« no previous file with comments | « test/NaCl/ARM/neon-vldlane-sandboxing.ll ('k') | test/NaCl/ARM/neon-vst2-sandboxing.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698