Rebased PNaCl localmods in LLVM to 223109

lib/Target/X86/X86InstrInfo.cpp

 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the X86 implementation of the TargetInstrInfo class.
@@ skipping 264 matching lines @@
   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
     unsigned RegOp = OpTbl2Addr[i].RegOp;
     unsigned MemOp = OpTbl2Addr[i].MemOp;
     unsigned Flags = OpTbl2Addr[i].Flags;
     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
                   RegOp, MemOp,
                   // Index 0, folded load and store, no alignment requirement.
                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
   }
 
+  // @LOCALMOD-BEGIN
+  uint16_t NoForwardForNaCl = STI.isTargetNaCl() ? TB_NO_FORWARD : 0;
+  // @LOCALMOD-END
+
   static const X86OpTblEntry OpTbl0[] = {
     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
-    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
-    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
+    { X86::CALL32r,     X86::CALL32m,       (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
+    { X86::CALL64r,     X86::CALL64m,       (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
-    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
-    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
+    { X86::JMP32r,      X86::JMP32m,        (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
+    { X86::JMP64r,      X86::JMP64m,        (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
@@ skipping 18 matching lines @@
     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
-    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
-    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
+    { X86::TAILJMPr,    X86::TAILJMPm,      (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
+    { X86::TAILJMPr64,  X86::TAILJMPm64,    (uint16_t)(TB_FOLDED_LOAD | NoForwardForNaCl) },
     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
     // AVX 128-bit versions of foldable instructions
     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
@@ skipping 2872 matching lines @@
 
   if (Opc) {
     BuildMI(MBB, MI, DL, get(Opc), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc));
     return;
   }
 
   // Moving EFLAGS to / from another register requires a push and a pop.
   // Notice that we have to adjust the stack if we don't want to clobber the
   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
+
+  // @LOCALMOD-BEGIN
+  //
+  // NaCl's sandbox doesn't allow usage of PUSHF/POPF. Instead use LAHF/SAHF
+  // which write the bottom 8 EFLAGS bits from/to AH.
+  bool FromEFLAGS = SrcReg == X86::EFLAGS;
+  bool ToEFLAGS = DestReg == X86::EFLAGS;
+  int Reg = FromEFLAGS ? DestReg : SrcReg;
+  bool is32 = X86::GR32RegClass.contains(Reg);
+  bool is64 = X86::GR64RegClass.contains(Reg);
+  int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
+  int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
+  int Pop = is64 ? X86::POP64r : X86::POP32r;
+  int AX = is64 ? X86::RAX : X86::EAX;
+  if ((FromEFLAGS || ToEFLAGS) && (is32 || is64) && Subtarget.isTargetNaCl()) {
+    BuildMI(MBB, MI, DL, get(Push)).addReg(AX);
+    if (FromEFLAGS) {
+      BuildMI(MBB, MI, DL, get(X86::LAHF));
+      BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
+    }
+    if (ToEFLAGS) {
+      BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
+      BuildMI(MBB, MI, DL, get(X86::SAHF));
+    }
+    BuildMI(MBB, MI, DL, get(Pop), AX);
+    return;
+  }
+  // @LOCALMOD-END
+
   if (SrcReg == X86::EFLAGS) {
     if (X86::GR64RegClass.contains(DestReg)) {
       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
       return;
     }
     if (X86::GR32RegClass.contains(DestReg)) {
       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
       return;
@@ skipping 2512 matching lines @@
       AU.setPreservesCFG();
       AU.addRequired<MachineDominatorTree>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
 }
 
 char LDTLSCleanup::ID = 0;
 FunctionPass*
 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }