Rebased PNaCl localmods in LLVM to 223109

lib/Target/X86/X86FastISel.cpp

 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the X86-specific support for the FastISel class. Much
@@ skipping 21 matching lines @@
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/GetElementPtrTypeIterator.h"
 #include "llvm/IR/GlobalAlias.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Operator.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/Statistic.h" // @LOCALMOD
 using namespace llvm;
 
+// @LOCALMOD-BEGIN
+#define DEBUG_TYPE "isel"
+STATISTIC(NumFastIselNaClFailures, "Number of instructions fast isel failed on for NaCl illegality");
+// @LOCALMOD-END
+
 namespace {
 
 class X86FastISel final : public FastISel {
   /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const X86Subtarget *Subtarget;
 
   /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
   /// floating point ops.
   /// When SSE is available, use it for f32 operations.
@@ skipping 440 matching lines @@
                                     unsigned &ResultReg) {
   unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
                            Src, /*TODO: Kill=*/false);
   if (RR == 0)
     return false;
 
   ResultReg = RR;
   return true;
 }
 
+/// @LOCALMOD-BEGIN
+/// isLegalAddressingModeForNaCl - Determine if the addressing mode is
+/// legal for NaCl translation.  If not, the caller is expected to
+/// reject the instruction for fast-ISel code generation.
+///
+/// The logic for the test is translated from the corresponding logic
+/// in X86DAGToDAGISel::LegalizeAddressingModeForNaCl().  It can't be
+/// used directly due to the X86AddressMode vs X86ISelAddressMode
+/// types.  As such, any changes to isLegalAddressingModeForNaCl() and
+/// X86DAGToDAGISel::LegalizeAddressingModeForNaCl() need to be
+/// synchronized.  The original conditions are indicated in comments.
+static bool isLegalAddressingModeForNaCl(const X86Subtarget *Subtarget,
+                                         const X86AddressMode &AM) {
+  if (Subtarget->isTargetNaCl64()) {
+    // Return true (i.e., is legal) if the equivalent of
+    // X86ISelAddressMode::isRIPRelative() is true.
+    if (AM.BaseType == X86AddressMode::RegBase &&
+        AM.Base.Reg == X86::RIP)
+      return true;
+
+    // Check for the equivalent of
+    // (!AM.hasBaseOrIndexReg() &&
+    //  !AM.hasSymbolicDisplacement() &&
+    //  AM.Disp < 0)
+    if (!((AM.BaseType == X86AddressMode::RegBase && AM.Base.Reg) ||
+          AM.IndexReg) &&
+        !AM.GV &&
+        AM.Disp < 0) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // At this point in the LegalizeAddressingModeForNaCl() code, it
+    // normalizes an addressing mode with a base register and no index
+    // register into an equivalent mode with an index register and no
+    // base register.  Since we don't modify AM, we may have to check
+    // both the base and index register fields in the remainder of the
+    // tests.
+
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::FrameIndexBase || AM.GV || AM.CP) &&
+    //   AM.IndexReg.getNode() &&
+    //   AM.Disp > 0)
+    // Note: X86AddressMode doesn't have a CP analogue
+    if ((AM.BaseType == X86AddressMode::FrameIndexBase || AM.GV) &&
+        ((AM.BaseType == X86AddressMode::RegBase && AM.Base.Reg) ||
+         AM.IndexReg) &&
+        AM.Disp > 0) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::RegBase) &&
+    //  AM.Base_Reg.getNode() &&
+    //  AM.IndexReg.getNode())
+    if ((AM.BaseType == X86AddressMode::RegBase) &&
+        AM.Base.Reg &&
+        AM.IndexReg) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+
+    // See X86DAGToDAGISel::FoldOffsetIntoAddress().
+    // Check for the equivalent of
+    // ((AM.BaseType == X86ISelAddressMode::RegBase ||
+    //   AM.BaseType == X86ISelAddressMode::FrameIndexBase) &&
+    //  (Val > 65535 || Val < -65536))
+    if ((AM.BaseType == X86AddressMode::RegBase ||
+         AM.BaseType == X86AddressMode::FrameIndexBase) &&
+        (AM.Disp > 65535 || AM.Disp < -65536)) {
+      ++NumFastIselNaClFailures;
+      return false;
+    }
+  }
+
+  return true;
+}
+
 bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) {
   // Handle constant address.
   if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
     // Can't handle alternate code models yet.
     if (TM.getCodeModel() != CodeModel::Small)
       return false;
 
     // Can't handle TLS yet.
     if (GV->isThreadLocal())
       return false;
@@ skipping 45 matching lines @@
 
         // Prepare for inserting code in the local-value area.
         SavePoint SaveInsertPt = enterLocalValueArea();
 
         if (TLI.getPointerTy() == MVT::i64) {
           Opc = X86::MOV64rm;
           RC  = &X86::GR64RegClass;
 
           if (Subtarget->isPICStyleRIPRel())
             StubAM.Base.Reg = X86::RIP;
+        // @LOCALMOD-BEGIN
+        } else if (Subtarget->isTargetNaCl64()) {
+          Opc = X86::MOV32rm;
+          RC  = &X86::GR32RegClass;
+
+          if (Subtarget->isPICStyleRIPRel())
+            StubAM.Base.Reg = X86::RIP;
+        // @LOCALMOD-END
         } else {
           Opc = X86::MOV32rm;
           RC  = &X86::GR32RegClass;
         }
 
         LoadReg = createResultReg(RC);
         MachineInstrBuilder LoadMI =
           BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
         addFullAddress(LoadMI, StubAM);
 
         // Ok, back to normal mode.
         leaveLocalValueArea(SaveInsertPt);
 
         // Prevent loading GV stub multiple times in same MBB.
         LocalValueMap[V] = LoadReg;
       }
 
       // Now construct the final address. Note that the Disp, Scale,
       // and Index values may already be set here.
       AM.Base.Reg = LoadReg;
       AM.GV = nullptr;
       return true;
     }
   }
 
   // If all else fails, try to materialize the value in a register.
   if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
+    // @LOCALMOD-START
+    if (Subtarget->isTargetNaCl64()) {
+      // We are about use a register in an addressing mode. However, x86-64
+      // NaCl does not allow arbitrary r+r addressing. One of the regs must
+      // be %r15 (inserted by the NaClRewritePass). Check that we will only
+      // end up with one reg defined after this.
+      if ((AM.Base.Reg == 0) && (AM.IndexReg == 0)) {
+        // Put into index register so that the NaCl rewrite pass will
+        // convert this to a 64-bit address.
+        AM.IndexReg = getRegForValue(V);
+        return AM.IndexReg != 0;
+      }
+      return false;
+    }
+    // @LOCALMOD-END
     if (AM.Base.Reg == 0) {
       AM.Base.Reg = getRegForValue(V);
       return AM.Base.Reg != 0;
     }
     if (AM.IndexReg == 0) {
       assert(AM.Scale == 1 && "Scale with no index!");
       AM.IndexReg = getRegForValue(V);
       return AM.IndexReg != 0;
     }
   }
 
   return false;
 }
 
 /// X86SelectAddress - Attempt to fill in an address from the given value.
 ///
+/// @LOCALMOD-BEGIN
+/// All "return v;" statements must be converted to
+/// "return (v) && isLegalAddressingModeForNaCl(Subtarget, AM);"
+/// except that "return false;" can of course be left unchanged.
+///
+/// Since X86SelectAddress() recursively builds up the AM result
+/// object, there is a risk that an intermediate result could be
+/// rejected in a situation where the final result was in fact legal,
+/// though it is hard to imagine this happening.
+/// @LOCALMOD-END
 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
   SmallVector<const Value *, 32> GEPs;
 redo_gep:
   const User *U = nullptr;
   unsigned Opcode = Instruction::UserOp1;
   if (const Instruction *I = dyn_cast<Instruction>(V)) {
     // Don't walk into other basic blocks; it's possible we haven't
     // visited them yet, so the instructions may not yet be assigned
     // virtual registers.
     if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) ||
@@ skipping 31 matching lines @@
     break;
 
   case Instruction::Alloca: {
     // Do static allocas.
     const AllocaInst *A = cast<AllocaInst>(V);
     DenseMap<const AllocaInst*, int>::iterator SI =
       FuncInfo.StaticAllocaMap.find(A);
     if (SI != FuncInfo.StaticAllocaMap.end()) {
       AM.BaseType = X86AddressMode::FrameIndexBase;
       AM.Base.FrameIndex = SI->second;
-      return true;
+      return isLegalAddressingModeForNaCl(Subtarget, AM); // @LOCALMOD
     }
     break;
   }
 
   case Instruction::Add: {
     // Adds of constants are common and easy enough.
     if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
       uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
       // They have to fit in the 32-bit signed displacement field though.
       if (isInt<32>(Disp)) {
@@ skipping 65 matching lines @@
     AM.Disp = (uint32_t)Disp;
     GEPs.push_back(V);
 
     if (const GetElementPtrInst *GEP =
           dyn_cast<GetElementPtrInst>(U->getOperand(0))) {
       // Ok, the GEP indices were covered by constant-offset and scaled-index
       // addressing. Update the address state and move on to examining the base.
       V = GEP;
       goto redo_gep;
     } else if (X86SelectAddress(U->getOperand(0), AM)) {
-      return true;
+      return isLegalAddressingModeForNaCl(Subtarget, AM); // @LOCALMOD
     }
 
     // If we couldn't merge the gep value into this addr mode, revert back to
     // our address and just match the value instead of completely failing.
     AM = SavedAM;
 
     for (SmallVectorImpl<const Value *>::reverse_iterator
            I = GEPs.rbegin(), E = GEPs.rend(); I != E; ++I)
       if (handleConstantAddresses(*I, AM))
-        return true;
+        return isLegalAddressingModeForNaCl(Subtarget, AM); // @LOCALMOD
 
     return false;
   unsupported_gep:
     // Ok, the GEP indices weren't all covered.
     break;
   }
   }
 
-  return handleConstantAddresses(V, AM);
+  // @LOCALMOD-START
+  if (handleConstantAddresses(V, AM))
+    return isLegalAddressingModeForNaCl(Subtarget, AM);
+  return false;
+  // @LOCALMOD-END
 }
 
 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
 ///
 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
   const User *U = nullptr;
   unsigned Opcode = Instruction::UserOp1;
   const Instruction *I = dyn_cast<Instruction>(V);
   // Record if the value is defined in the same basic block.
   //
@@ skipping 243 matching lines @@
 
   // The x86-64 ABI for returning structs by value requires that we copy
   // the sret argument into %rax for the return. We saved the argument into
   // a virtual register in the entry block, so now we copy the value out
   // and into %rax. We also do the same with %eax for Win32.
   if (F.hasStructRetAttr() &&
       (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
     unsigned Reg = X86MFInfo->getSRetReturnReg();
     assert(Reg &&
            "SRetReturnReg should have been set in LowerFormalArguments()!");
-    unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
+    // @LOCALMOD-BEGIN -- Ensure that the register classes match.
+    // At this point, SRetReturnReg is EDI, because PointerTy() for NaCl
+    // is i32.  We then copy to EAX instead of RAX.  Alternatively, we could
+    // have zero-extended EDI to RDI then copy to RAX, but this has a smaller
+    // encoding (2 bytes vs 3 bytes).
+    unsigned CopyTo = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
-            RetReg).addReg(Reg);
-    RetRegs.push_back(RetReg);
+            CopyTo).addReg(Reg);
+    // @LOCALMOD-END
   }
 
   // Now emit the RET.
   MachineInstrBuilder MIB =
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
   for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
     MIB.addReg(RetRegs[i], RegState::Implicit);
   return true;
 }
 
@@ skipping 1054 matching lines @@
   // We don't care about alignment here since we just emit integer accesses.
   while (Len) {
     MVT VT;
     if (Len >= 8 && i64Legal)
       VT = MVT::i64;
     else if (Len >= 4)
       VT = MVT::i32;
     else if (Len >= 2)
       VT = MVT::i16;
     else {
+      assert(Len == 1);
       VT = MVT::i8;
     }
 
     unsigned Reg;
     bool RV = X86FastEmitLoad(VT, SrcAM, nullptr, Reg);
     RV &= X86FastEmitStore(VT, Reg, /*Kill=*/true, DestAM);
     assert(RV && "Failed to emit load or store??");
 
     unsigned Size = VT.getSizeInBits()/8;
     Len -= Size;
@@ skipping 17 matching lines @@
 
     unsigned Opc;
     const TargetRegisterClass *RC = nullptr;
 
     switch (VT.SimpleTy) {
     default: llvm_unreachable("Invalid result type for frameaddress.");
     case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
     case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
     }
 
-    // This needs to be set before we call getFrameRegister, otherwise we get
-    // the wrong frame register.
+    // This needs to be set before we call getPtrSizedFrameRegister, otherwise
+    // we get the wrong frame register.
     MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
     MFI->setFrameAddressIsTaken(true);
 
     const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
         TM.getSubtargetImpl()->getRegisterInfo());
-    unsigned FrameReg = RegInfo->getFrameRegister(*(FuncInfo.MF));
+    unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*(FuncInfo.MF));
     assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
             (FrameReg == X86::EBP && VT == MVT::i32)) &&
            "Invalid Frame Register!");
 
     // Always make a copy of the frame register to to a vreg first, so that we
     // never directly reference the frame register (the TwoAddressInstruction-
     // Pass doesn't like that).
     unsigned SrcReg = createResultReg(RC);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
             TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
@@ skipping 728 matching lines @@
     GV = CalleeAM.GV;
   } else if (CalleeAM.Base.Reg != 0) {
     CalleeOp = CalleeAM.Base.Reg;
   } else
     return false;
 
   // Issue the call.
   MachineInstrBuilder MIB;
   if (CalleeOp) {
     // Register-indirect call.
-    unsigned CallOpc = Is64Bit ? X86::CALL64r : X86::CALL32r;
+    unsigned CallOpc;
+    if (Subtarget->is64Bit()) {
+      // @LOCALMOD-BEGIN: zero extend the register like in the non-O0 case:
+      // http://reviews.llvm.org/D5355
+      // TODO: upstream this for x32 also (add a test).
+      if (Subtarget->isTarget64BitILP32()) {
+        unsigned CalleeOp32 = CalleeOp;
+        CalleeOp = createResultReg(&X86::GR64RegClass);
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+                TII.get(TargetOpcode::SUBREG_TO_REG), CalleeOp)
+            .addImm(0).addReg(CalleeOp32).addImm(X86::sub_32bit);
+      }
+      // @LOCALMOD-END
+      CallOpc = X86::CALL64r;
+    } else
+      CallOpc = X86::CALL32r;
     MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
       .addReg(CalleeOp);
   } else {
     // Direct call.
     assert(GV && "Not a direct call");
-    unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
+    unsigned CallOpc;
+    if (Subtarget->is64Bit())
+      CallOpc = Subtarget->isTargetNaCl() ? X86::NACL_CG_CALL64pcrel32 : X86::CALL64pcrel32; // @LOCALMOD
+    else
+      CallOpc = X86::CALLpcrel32;
 
     // See if we need any target-specific flags on the GV operand.
     unsigned char OpFlags = 0;
 
     // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
     // external symbols most go through the PLT in PIC mode.  If the symbol
     // has hidden or protected visibility, or if it is static or local, then
     // we don't need to use the PLT - we can directly call it.
     if (Subtarget->isTargetELF() &&
         TM.getRelocationModel() == Reloc::PIC_ &&
@@ skipping 427 matching lines @@
   return true;
 }
 
 
 namespace llvm {
   FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
                                 const TargetLibraryInfo *libInfo) {
     return new X86FastISel(funcInfo, libInfo);
   }
 }