Rebased PNaCl localmods in LLVM to 223109

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/X86BaseInfo.h"
 #include "MCTargetDesc/X86FixupKinds.h"
+#include "MCTargetDesc/X86MCNaCl.h" // @LOCALMOD
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionCOFF.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSectionMachO.h"
@@ skipping 83 matching lines @@
     return Infos[Kind - FirstTargetFixupKind];
   }
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value, bool IsPCRel) const override {
     unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
 
     assert(Fixup.getOffset() + Size <= DataSize &&
            "Invalid fixup offset!");
 
+    // @LOCALMOD-BEGIN
+    // This check breaks negative addends on x86-32.  It makes x86-32
+    // behaviour inconsistent with x86-64 and ARM.
+    // See: https://code.google.com/p/nativeclient/issues/detail?id=3548
+#if 0
     // Check that uppper bits are either all zeros or all ones.
     // Specifically ignore overflow/underflow as long as the leakage is
     // limited to the lower bits. This is to remain compatible with
     // other assemblers.
     assert(isIntN(Size * 8 + 1, Value) &&
            "Value does not fit in the Fixup field");
+#endif
+    // @LOCALMOD-END
 
     for (unsigned i = 0; i != Size; ++i)
       Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
   }
 
   bool mayNeedRelaxation(const MCInst &Inst) const override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
@@ skipping 248 matching lines @@
 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
 public:
   ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
     : ELFX86AsmBackend(T, OSABI, CPU) {}
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
   }
 };
 
+// @LOCALMOD-BEGIN
+class NaClX86_32AsmBackend : public ELFX86_32AsmBackend {
+public:
+  NaClX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
+      : ELFX86_32AsmBackend(T, OSABI, CPU),
+        STI(X86_MC::createX86MCSubtargetInfo("i386-unknown-nacl", CPU, "")) {
+    State.PrefixSaved = 0;
+    State.PrefixPass = false;
+    State.EmitRaw = false;
+  }
+  ~NaClX86_32AsmBackend() override {}
+
+  bool CustomExpandInst(const MCInst &Inst, MCStreamer &Out) override {
+    return CustomExpandInstNaClX86(*STI, Inst, Out, State);
+  }
+
+private:
+  std::unique_ptr<MCSubtargetInfo> STI;
+  X86MCNaClSFIState State;
+};
+
+class NaClX86_64AsmBackend : public ELFX86_64AsmBackend {
+public:
+  NaClX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
+      : ELFX86_64AsmBackend(T, OSABI, CPU),
+        STI(X86_MC::createX86MCSubtargetInfo("x86_64-unknown-nacl", CPU, "")) {
+    State.PrefixSaved = 0;
+    State.PrefixPass = false;
+    State.EmitRaw = false;
+  }
+  ~NaClX86_64AsmBackend() override {}
+
+  bool CustomExpandInst(const MCInst &Inst, MCStreamer &Out) override {
+    return CustomExpandInstNaClX86(*STI, Inst, Out, State);
+  }
+
+private:
+  std::unique_ptr<MCSubtargetInfo> STI;
+  X86MCNaClSFIState State;
+};
+// @LOCALMOD-END
+
 class WindowsX86AsmBackend : public X86AsmBackend {
   bool Is64Bit;
 
 public:
   WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
     : X86AsmBackend(T, CPU)
     , Is64Bit(is64Bit) {
   }
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
@@ skipping 426 matching lines @@
                                            StringRef CPU) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSBinFormatMachO())
     return new DarwinX86_32AsmBackend(T, MRI, CPU);
 
   if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, false, CPU);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
+  // @LOCALMOD-BEGIN
+  if (TheTriple.isOSNaCl())
+    return new NaClX86_32AsmBackend(T, OSABI, CPU);
+  // @LOCALMOD-END
   return new ELFX86_32AsmBackend(T, OSABI, CPU);
 }
 
 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
                                            const MCRegisterInfo &MRI,
                                            StringRef TT,
                                            StringRef CPU) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSBinFormatMachO()) {
     MachO::CPUSubTypeX86 CS =
         StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
             .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
             .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
     return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
   }
 
   if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
     return new WindowsX86AsmBackend(T, true, CPU);
 
   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
 
+  // @LOCALMOD-BEGIN
+  if (TheTriple.isOSNaCl())
+    return new NaClX86_64AsmBackend(T, OSABI, CPU);
+  // @LOCALMOD-END
   if (TheTriple.getEnvironment() == Triple::GNUX32)
     return new ELFX86_X32AsmBackend(T, OSABI, CPU);
   return new ELFX86_64AsmBackend(T, OSABI, CPU);
 }