Rebased PNaCl localmods in LLVM to 223109

lib/Target/Mips/MipsSEISelLowering.cpp

 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // Subclass of MipsTargetLowering specialized for mips32/64.
@@ skipping 1490 matching lines @@
   return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
 }
 
 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                       SelectionDAG &DAG) const {
   SDLoc DL(Op);
 
   switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
   default:
     return SDValue();
+  // @LOCALMOD-BEGIN
+  case Intrinsic::nacl_read_tp:
+    return GetNaClThreadPointer(DAG, SDLoc(Op));
+  // @LOCALMOD-END
   case Intrinsic::mips_shilo:
     return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
   case Intrinsic::mips_dpau_h_qbl:
     return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
   case Intrinsic::mips_dpau_h_qbr:
     return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
   case Intrinsic::mips_dpsu_h_qbl:
     return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
   case Intrinsic::mips_dpsu_h_qbr:
     return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
@@ skipping 1718 matching lines @@
   BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
 
   // Emit 1.0 * fexp2(Wt)
   BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
       .addReg(Ws2)
       .addReg(MI->getOperand(1).getReg());
 
   MI->eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }