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| 1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===// | 1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===// |
| 2 // | 2 // |
| 3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file contains a pass that performs load / store related peephole | 10 // This file contains a pass that performs load / store related peephole |
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| 1064 /// | 1064 /// |
| 1065 /// stmia rn, <ra, rb, rc> | 1065 /// stmia rn, <ra, rb, rc> |
| 1066 /// rn := rn + 4 * 3; | 1066 /// rn := rn + 4 * 3; |
| 1067 /// => | 1067 /// => |
| 1068 /// stmia rn!, <ra, rb, rc> | 1068 /// stmia rn!, <ra, rb, rc> |
| 1069 /// | 1069 /// |
| 1070 /// rn := rn - 4 * 3; | 1070 /// rn := rn - 4 * 3; |
| 1071 /// ldmia rn, <ra, rb, rc> | 1071 /// ldmia rn, <ra, rb, rc> |
| 1072 /// => | 1072 /// => |
| 1073 /// ldmdb rn!, <ra, rb, rc> | 1073 /// ldmdb rn!, <ra, rb, rc> |
| 1074 /// @LOCALMOD This is especially useful for rn == sp |
| 1074 bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB, | 1075 bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB, |
| 1075 MachineBasicBlock::iterator MBBI, | 1076 MachineBasicBlock::iterator MBBI, |
| 1076 bool &Advance, | 1077 bool &Advance, |
| 1077 MachineBasicBlock::iterator &I) { | 1078 MachineBasicBlock::iterator &I) { |
| 1078 // Thumb1 is already using updating loads/stores. | 1079 // Thumb1 is already using updating loads/stores. |
| 1079 if (isThumb1) return false; | 1080 if (isThumb1) return false; |
| 1080 | 1081 |
| 1081 MachineInstr *MI = MBBI; | 1082 MachineInstr *MI = MBBI; |
| 1082 unsigned Base = MI->getOperand(0).getReg(); | 1083 unsigned Base = MI->getOperand(0).getReg(); |
| 1083 bool BaseKill = MI->getOperand(0).isKill(); | 1084 bool BaseKill = MI->getOperand(0).isKill(); |
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| 1748 /// MergeReturnIntoLDM - If this is a exit BB, try merging the return ops | 1749 /// MergeReturnIntoLDM - If this is a exit BB, try merging the return ops |
| 1749 /// ("bx lr" and "mov pc, lr") into the preceding stack restore so it | 1750 /// ("bx lr" and "mov pc, lr") into the preceding stack restore so it |
| 1750 /// directly restore the value of LR into pc. | 1751 /// directly restore the value of LR into pc. |
| 1751 /// ldmfd sp!, {..., lr} | 1752 /// ldmfd sp!, {..., lr} |
| 1752 /// bx lr | 1753 /// bx lr |
| 1753 /// or | 1754 /// or |
| 1754 /// ldmfd sp!, {..., lr} | 1755 /// ldmfd sp!, {..., lr} |
| 1755 /// mov pc, lr | 1756 /// mov pc, lr |
| 1756 /// => | 1757 /// => |
| 1757 /// ldmfd sp!, {..., pc} | 1758 /// ldmfd sp!, {..., pc} |
| 1759 // @LOCALMOD for sfi we do not want this to happen |
| 1758 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { | 1760 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { |
| 1761 // @LOCALMOD-START |
| 1762 // For NaCl, do not load into PC directly for a return, since NaCl requires |
| 1763 // masking the address first. |
| 1764 if (STI->isTargetNaCl()) { |
| 1765 return false; |
| 1766 } |
| 1767 // @LOCALMOD-END |
| 1768 |
| 1759 // Thumb1 LDM doesn't allow high registers. | 1769 // Thumb1 LDM doesn't allow high registers. |
| 1760 if (isThumb1) return false; | 1770 if (isThumb1) return false; |
| 1761 if (MBB.empty()) return false; | 1771 if (MBB.empty()) return false; |
| 1762 | 1772 |
| 1763 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); | 1773 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); |
| 1764 if (MBBI != MBB.begin() && | 1774 if (MBBI != MBB.begin() && |
| 1765 (MBBI->getOpcode() == ARM::BX_RET || | 1775 (MBBI->getOpcode() == ARM::BX_RET || |
| 1766 MBBI->getOpcode() == ARM::tBX_RET || | 1776 MBBI->getOpcode() == ARM::tBX_RET || |
| 1767 MBBI->getOpcode() == ARM::MOVPCLR)) { | 1777 MBBI->getOpcode() == ARM::MOVPCLR)) { |
| 1768 MachineInstr *PrevMI = std::prev(MBBI); | 1778 MachineInstr *PrevMI = std::prev(MBBI); |
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| 2268 } | 2278 } |
| 2269 | 2279 |
| 2270 | 2280 |
| 2271 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store | 2281 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store |
| 2272 /// optimization pass. | 2282 /// optimization pass. |
| 2273 FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) { | 2283 FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) { |
| 2274 if (PreAlloc) | 2284 if (PreAlloc) |
| 2275 return new ARMPreAllocLoadStoreOpt(); | 2285 return new ARMPreAllocLoadStoreOpt(); |
| 2276 return new ARMLoadStoreOpt(); | 2286 return new ARMLoadStoreOpt(); |
| 2277 } | 2287 } |
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