MIPS: [turbofan] Optimize certain chains of Branch into a Switch.

src/compiler/mips64/code-generator-mips64.cc

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 266c0b4f5629a88c77c1c65d71e68bff5bef1088..7c1288d7549849cae10a892af9862fe0f528747d 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -428,8 +428,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kArchJmp:
       AssembleArchJump(i.InputRpo(0));
       break;
-    case kArchSwitch:
-      AssembleArchSwitch(instr);
+    case kArchLookupSwitch:
+      AssembleArchLookupSwitch(instr);
+      break;
+    case kArchTableSwitch:
+      AssembleArchTableSwitch(instr);
       break;
     case kArchNop:
       // don't emit code for nops.
@@ -919,32 +922,6 @@ void CodeGenerator::AssembleArchJump(BasicBlock::RpoNumber target) {
 }
 
 
-void CodeGenerator::AssembleArchSwitch(Instruction* instr) {
-  MipsOperandConverter i(this, instr);
-  int const kNumLabels = static_cast<int>(instr->InputCount() - 1);
-  v8::internal::Assembler::BlockTrampolinePoolScope block_trampoline_pool(
-      masm());
-  Label here;
-
-  // Ensure that dd-ed labels goes to 8 byte aligned addresses.
-  if ((masm()->pc_offset() & 7) == 0) {
-    __ nop();
-  }
-  __ bal(&here);
-  __ nop();  // Branch delay slot nop.
-  __ bind(&here);
-  __ dsll(at, i.InputRegister(0), 3);
-  __ daddu(at, at, ra);
-  __ ld(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
-  __ jr(at);
-  __ nop();  // Branch delay slot nop.
-
-  for (int index = 0; index < kNumLabels; ++index) {
-    __ dd(GetLabel(i.InputRpo(index + 1)));
-  }
-}
-
-
 // Assembles boolean materializations after an instruction.
 void CodeGenerator::AssembleArchBoolean(Instruction* instr,
                                         FlagsCondition condition) {
@@ -1063,6 +1040,42 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
 }
 
 
+void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
+  MipsOperandConverter i(this, instr);
+  Register input = i.InputRegister(0);
+  for (size_t index = 2; index < instr->InputCount(); index += 2) {
+    __ Branch(GetLabel(i.InputRpo(index + 1)), eq, input,
+              Operand(i.InputInt32(index + 0)));
+  }
+  AssembleArchJump(i.InputRpo(1));
+}
+
+
+void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
+  MipsOperandConverter i(this, instr);
+  Register input = i.InputRegister(0);
+  size_t const case_count = instr->InputCount() - 2;
+  Label here;
+
+  __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
+  // Ensure that dd-ed labels goes to 8 byte aligned addresses.

[paul.l..., 2015/02/17 19:33:59]

nit: "goes to ... " should probably be "use 8 byte aligned locations" 

+  if ((masm()->pc_offset() & 7) == 0) {
+    __ nop();
+  }
+  __ bal(&here);

[paul.l..., 2015/02/17 19:33:59]

Add BlockTrampolinePoolFor() to cover table and indexing into it.

+  __ nop();  // Branch delay slot nop.
+  __ bind(&here);
+  __ dsll(at, input, 3);
+  __ daddu(at, at, ra);
+  __ ld(at, MemOperand(at, 5 * v8::internal::Assembler::kInstrSize));
+  __ jr(at);
+  __ nop();  // Branch delay slot nop.
+  for (size_t index = 0; index < case_count; ++index) {
+    __ dd(GetLabel(i.InputRpo(index + 2)));
+  }
+}
+
+
 void CodeGenerator::AssembleDeoptimizerCall(int deoptimization_id) {
   Address deopt_entry = Deoptimizer::GetDeoptimizationEntry(
       isolate(), deoptimization_id, Deoptimizer::LAZY);